The size of the wordline driver in Wada's model is independent of the number of cells attached to the wordline; this severely overestimates the wordline delay of large arrays. Our model assumes a variable-sized wordline driver. Normally, a cache designer would choose a target wordline rise time, and adjust the driver size appropriately. Rather than assuming a constant rise time for caches of all sizes, however, we assume the desired rise time (to a 50% word line swing) is:
where
and
is a constant that depends on the
implementation technology. To obtain the transistor size that
would give this rise time, it is necessary to work backwards,
using an equivalent RC circuit to find the required driver resistance,
and then finding the transistor width that would give this resistance.
This is described in Section 5.5.