There are two potential critical paths in a cache read access. If the time to read the tag array, perform the comparison, and drive the multiplexor select signals is larger than the time to read the data array, then the tag side is the critical path, while if it takes longer to read the data array, then the data side is the critical path. In many cache implementations, the designer would try to margin the cache design such that the tag path is slightly faster than the data path so that the multiplexor select signals are valid by the time the data is ready. Often, however, this is not possible. Therefore, either side could determine the access time, meaning both sides must be modeled in detail.
In a direct-mapped cache, the access time is the larger of the two paths:
where 
is the delay of the decoder, wordline, bitline, and
sense amplifier for the data array, 
is the delay of the
decoder, wordline, bitline, sense amplifier, and comparator for the
tag array, 
is the delay of the cache data output driver,
and 
is the delay of the valid signal driver.
In a set-associative cache, the tag array must be read before the data signals can be driven. Thus, the access time is:
where 
is the same as , except that it
includes the time to drive the select lines of the output multiplexors.
Figures 13 to 16 show analytical and
Hspice estimations of the data and tag sides for direct-mapped and 4-way
set-associative caches.
A 
CMOS process was assumed [6].
To gather these results, the model was first used
to find the array organization parameters
which resulted in the lowest access time
via exhaustive search for
each cache size. These optimum parameters are shown in the figures (the six
numbers associated with each point correspond to 
, 
,
, 
, 
, and 
in that order). The
parameters were then used in the Hspice model. As the graphs show, the
difference between the analytical and Hspice results is less than 6% in
every case.
Figure: 4-way set associative: 
Figure: 4-way set associative: 
