References

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2

T. Wada, S. Rajan, and S. A. Przybylski, ``An analytical access time model for on-chip cache memories,'' IEEE Journal of Solid-State Circuits, Vol. 27, No. 8, pp. 1147-1156, Aug. 1992.

3

S. J. Wilton and N. P. Jouppi, ``An access and cycle time model for on-chip caches,'' Tech. Rep. 93/5, Digital Equipment Corporation Western Research Lab, 1994.

4

M. A. Horowitz, ``Timing models for mos circuits,'' Tech. Rep. Technical Report SEL83-003, Integrated Circuits Laboratory, Stanford University, 1983.

5

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6

M. G. Johnson and N. P. Jouppi, ``Transistor model for a synthetic 0.8um CMOS process,'' Class notes for Stanford University EE371, Spring 1990.

7

R. J. Proebsting, ``Post charge logic permits 4ns 18K CMOS RAM.'' 1987.

8

T. I. Chappell, B. A. Chappel, S. E. Schuster, J. W. Allen, S. P. Klepner, R. V. Joshi, and R. L. Franch, ``A 2ns cycle, 3.8ns access 512kb CMOS ECL RAM with a fully pipelined architecture,'' IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, pp. 1577-1585, Nov. 1991.

9

N. P. Jouppi and S. J. Wilton, ``Tradeoffs in two-level on-chip caching,'' in Proceedings of the 21th Annual International Symposium on Computer Architecture, pp. 34-45, April 1994.