|
|
|||||||||||||||||
|
|||||||||||||||||
|
|
|
||||||||||||||||
|
PUBLICATIONS Journals [1]
C.
Grecu, A. Ivanov, R.
Saleh, P.P. Pande, "Testing Networks-on-chip Communication
Infrastructures", to appear, IEEE Transactions on Computer Aided Design
(accepted April 2007). [2]
A.
Ganguly, P. P. Pande, C.
Grecu, “Design of Low Power & Reliable Networks on Chip Through
Joint
Crosstalk Avoidance and Multiple Error Correction Coding”, to appear,
Journal
of Electronic Testing, Theory and Applications JETTA (accepted June
2007). [3]
P. P.
Pande, A. Ganguly, H.
Zhu, C. Grecu, “Energy Reduction through Crosstalk Avoidance Coding in
Networks
on Chip”, to appear, Journal of Systems Architecture, Elsevier
(accepted August
2007). [4]
R. B.
Foist, C. Grecu, A.
Ivanov, R. F. Turner, “An FPGA Design Project: Creating a PowerPC
Subsystem
plus User Logic”, to appear, IEEE Transactions on Education (accepted
August
2007). [5]
R.
Saleh, S. Wilton, S. Mirabbasi,
A. Hu, M. Greenstreet, P. P. Pande, C. Grecu, A. Ivanov, “System on
Chip: Reuse
and Integration ”, Proceedings of the IEEE, Vol. 94, Issue 6, June
2006,
pp.
1050-1069. [6]
P. P.
Pande, C. Grecu, M.
Jones, A. Ivanov, R. Saleh, "Performance Evaluation and Design
Trade-offs
for MP-SoC Interconnect Architectures”, IEEE Transactions on Computers,
vol. 54
(8), 2005, pp. 1025-1040. [7]
C.
Grecu, P. P. Pande , A.
Ivanov, R. Saleh, "Timing Analysis of Network on Chip Architectures for
MP-SoC Platforms", Microelectronics Journal, Elsevier, Volume 36, Issue
9,
September 2005, pp. 833-845. [8]
P. P.
Pande, C. Grecu,André
Ivanov, Res Saleh, Giovanni De Micheli, "Design, Synthesis and Test of
Networks on Chip: Challenges and Solutions", IEEE Design and Test of
Computers, vol. 22, no. 5,
Sept/Oct, 2005, pp.
404-413.
[1]
H. Zhu,
P. P. Pande, C.
Grecu, "Performance evaluation of adaptive routing algorithms for
achieving fault tolerance in NoC fabrics," IEEE International
Conference
on Application-specific Systems, Architectures and Processors, ASAP
2007, July
9th - 11th , 2007. [2]
C.
Grecu, L. Anghel, P. P.
Pande, A. Ivanov, R. Saleh, "Essential fault-tolerance metrics for NoC
infrastructures",
IEEE International Online Testing Symposium (IOLTS), 9th -11th
July, 2007 [3]
P. P.
Pande, A. Ganguly, B.
Feero, C. Grecu, "Applicability of energy efficient coding methodology
to
address signal integrity in 3D NoC fabrics", IEEE International Online
Testing Symposium (IOLTS), 9th -11th July, 2007. [4]
A.
Ganguly, P. P. Pande, B.
Belzer, C. Grecu, "Addressing signal integrity in networks-on-chip
interconnects through crosstalk-aware double error correction coding",
Proceedings of IEEE Computer Society
Annual Symposium on VLSI (ISVLSI), 9th -11th May
2007. [5]
C.
Grecu, A. Ivanov, P.P.
Pande, A. Jantsch, E. Salminen, U. Ogras, R. Marculescu, "Towards open
network-on-chip benchmarks", Proceedings of The 1st
ACM/IEEE International Symposium on
Networks-on-Chip, May, 2007. [6]
C.
Grecu, A. Ivanov, R.
Saleh, E. S. Sogomonyan, P.P. Pande, "On-line fault detection and
location
for NoC interconnects", 12th IEEE International Symposium on On-Line
Testing, IOLTS06, July 2006, pp: 145 - 150 [7]
C.
Grecu, A. Ivanov, R.
Saleh, P.P. Pande, "NoC interconnect yield improvement using crosspoint
redundancy", IEEE Sypmosium on Defect and Fault Tolerance in VLSI
Systems,
2006, DFT '06, Oct. 2006, pp:457 – 465. [8]
P. P.
Pande, A. Ganguly, B.
Feero, B. Belzer, C. Grecu, "Design of low power and reliable networks
on
chip through joint crosstalk avoidance and forward error correction
coding", IEEE International Symposium on Defect and Fault Tolerance in
VLSI Systems (DFT'06), 2nd - 4th
October 2006. [9]
P. P.
Pande, H. Zhu, A.
Ganguly, C. Grecu, "Crosstalk-aware energy reduction in NoC
communication
fabrics", IEEE International SOC Conference, SOCC 2006, [10]
P. P.
Pande, H. Zhu, A.
Ganguly, C. Grecu, “Energy reduction through crosstalk avoidance coding
in NoC
paradigm” Euromicro Conference on Digital System Design, DSD 2006, 30th
August-1st September
2006. [11]
C.
Grecu, P. P. Pande, A.
Ivanov, R. Saleh, " BIST for network on chip interconnect
infrastructures", IEEE VLSI Test Symposium, VTS 2006, 30th
April
– 4th May, 2006. [12]
C.
Grecu, P. P. Pande, B.
Wang, A. Ivanov, R. Saleh, "Methodologies and algorithms for testing
switch-based NoC interconnects ", IEEE International Symposium on
Defect
and Fault Tolerance in VLSI Systems (DFT 2005), 3-5th October, 2005, Monterey, USA. [13]
P. P.
Pande, C. Grecu, M.
Jones, A. Ivanov, R. Saleh, “Effect of traffic localization on energy
dissipation in NoC-based interconnect infrastructures”, IEEE
International
Symposium on Circuits and Systems, ISCAS 2005, 23-26th May,
Kobe,
Japan. [14]
P. P.
Pande, C. Grecu, M.
Jones, A. Ivanov, R. Saleh, "Evaluation of MP-SoC interconnect
architectures:
A Case Study", Proceedings of 4th IEEE International
Workshop
on Systems-on-Chip IWSOC, 19th -21st July, [15]
C.
Grecu, P. P. Pande, A.
Ivanov, R. Saleh, "Structured interconnect architecture: a solution for
the non-scalability of bus-based SoCs", The Great Lakes Symposium on
VLSI
GLSVLSI 2004, 26-28th April, [16]
C.
Grecu, P. P. Pande, A.
Ivanov, R. Saleh, "A scalable communication-centric SoC interconnect
architecture", Proceedings of IEEE International Symposium on Quality
Electronic
Design, ISQED 2004, San Jose, California, USA, 22-24th
March, 2004. [17]
P. P.
Pande, C. Grecu, A.
Ivanov, R. Saleh, "Design of a switch for network on chip
applications",
IEEE International Symposium on Circuits and Systems, ISCAS 2003, vol.
V, pp. 217-220,
Bangkok, Thailand. [18]
P. P.
Pande, C. Grecu, A.
Ivanov, R. Saleh, "Switch-based interconnect architecture for future
systems on chip", SPIE, VLSI Circuits and Systems, vol. 5117, pp.
228-237,
2003, Maspalomas, [19]
P. P.
Pande, C. Grecu, A.
Ivanov, R. Saleh, "High-throughput switch-based interconnect for future
SoCs",
The 3rd IEEE International Workshop on Systems-on-Chip IWSOC
2003,
pp. 304-310, 2003, Other contributions: [1]
C.
Grecu, A. Ivanov, P. P. Pande, A. Jantsch, E. Salminen, U. Ogras, R.
Marculescu,
“An initiative towards open network-on-chip benchmarks”, white paper, http://www.ocpip.org/socket/whitepapers/NoC-Benchmarks-WhitePaper-15.pdf,
2007. [2]
C. Grecu, P. P. Pande, A. Ivanov, R. Saleh, “Making
networks-on-chip
happen”, Electronic Design Automation Technology Forum, June 2005. [3]
A. Ivanov, R.
Saleh, P. P. Pande, C. Grecu,
“A 'network-centric' approach to on-chip interconnect”. Article
published in EETimes
Design News, May
2004. [4]
C. Grecu, P. P.
Pande, A. Ivanov, R. Saleh,
“Design and test of networks-on-chip”. Micronet R&D Annual
Workshop, 2005, [5]
C. Grecu, P.P. Pande, A. Ivanov,
R. Saleh, “A highly
pipelined network-on-chip for multi-core SoC platforms”. Micronet
R&D
Annual Workshop, 2004, [6]
P. P. Pande,
C. Grecu,
A.
Ivanov, R. Saleh, “High throughput
interconnect architecture for future SoCs”. Micronet R&D Annual
Workshop,
2003, Presentations:
|
||||||||||||||||
|
|
UBC Faculty of Electrical and
Computer Engineering
|
||||||||||||||||
