Ed Casas (edc@ece.ubc.ca) Thu, 18 Feb 1999 16:06:31 -0800
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Date: Thu, 18 Feb 1999 16:06:31 -0800 From: Ed Casas <edc@ece.ubc.ca> Subject: Re: Assignment 3A student asked: > I'm a little confused about the memory component - > do we have an output enable? No. This memory has separate data-in and data-out signals so no output enable is required. > is the write synchronous? Yes. -- Ed Casas edc@ece.ubc.ca http://casas.ece.ubc.ca +1 604 822-2592
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