corrections to Assignment 3

Ed Casas (edc@ece.ubc.ca) Fri, 19 Feb 1999 16:51:29 -0800 

Date: Fri, 19 Feb 1999 16:51:29 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: corrections to Assignment 3



		  Corrections for Assignment 3:

Assignment 3, part 1 is due on February 26 (8:30 AM).

Your top-level design will have to include a multiplexer for the
two memory address sources (the PC and I registers). You will
also have to add a "fetch" output to the controller to indicate
the type of cycle (fetch or execute) and control this
multiplexer.  During the fetch cycle the address is supplied by
the PC register and during the execute cycle the address is
supplied by the I register.

The reset signal should be an input to the controller, not the PC
datapath.

conv_integer() does not accept std_logic_vector arguments, you
must use conv_integer(unsigned(x)).

JNZ is "Jump on Not Zero".

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592