Lab 4

Marc Lee (wnmlee@ece.ubc.ca) Sun, 19 Nov 2000 17:30:03 -0800

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From: "Marc Lee" <wnmlee@ece.ubc.ca>
Subject: Lab 4
Date: Sun, 19 Nov 2000 17:30:03 -0800



Hi,

Is reset synchronous to the output of the clock divider? In other words, do we reset the 3-bit counter only when the output of the clock divider is high?


Marc

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