Re: Lab4

Yiu Simon (simonyiu@yahoo.com) Sun, 19 Nov 2000 22:49:04 -0800 (PST) 

Date: Sun, 19 Nov 2000 22:49:04 -0800 (PST)
From: Yiu Simon <simonyiu@yahoo.com>
Subject: Re: Lab4



Marc:

synchronous to the 8.333Mhz clock and it should reset
to 0 whenever the status register at 220H is read. 
Only in this way, the interrupt can be generated in
every 4 seconds.  Otherwise, if the 3-bit counter
reset to 0 after the clock divider output a high,
there would be a one second delay and the interrupt
will be generated every 5 seconds.  

Yiu, Tik Kong Simon

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