Ed Casas (edc@ece.ubc.ca) Mon, 20 Nov 2000 16:49:27 -0800
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
- New Message to:eece379@listhost.ece.ubc.ca
- Reply to:Re: Lab 4
- Next message: Ed Casas: "Re: Lab4"
- Previous message: Yiu Simon: "Re: Lab 4"
- Maybe in reply to: Marc Lee: "Lab 4"
Date: Mon, 20 Nov 2000 16:49:27 -0800 From: Ed Casas <edc@ece.ubc.ca> Subject: Re: Lab 4> Is reset synchronous to the output of the clock divider? Not in the sense that the clock divider output acts as a clock. > In other words, do we reset the 3-bit counter only when the > output of the clock divider is high? No. You reset it when the CPU does a read from the appropriate address. -- Ed Casas edc@ece.ubc.ca http://casas.ece.ubc.ca +1 604 822-2592
- Next message: Ed Casas: "Re: Lab4"
- Previous message: Yiu Simon: "Re: Lab 4"
- Maybe in reply to: Marc Lee: "Lab 4"