Re: Asgn#3:Clock signal for RAM component

Ed Casas (edc@ece.ubc.ca) Fri, 3 Nov 2000 10:01:30 -0800 

Date: Fri, 3 Nov 2000 10:01:30 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Asgn#3:Clock signal for RAM component



> "Each of the 32x8=256 flip-flops in the RAM is indeed reloaded
> on each rising edge of the clock...
> 
> Why is it necessary to load EACH of the 32 RAM registers on the
> rise of the clock?

A synchronous design requires that all FFs in the circuit have a
common clock.  The only way to prevent a FF from being loaded is
to "gate" the clock.  This would result in an asynchronous design
whose timing performance would be difficult to analyze.

If we were worried about power consumption we would use a
different design method for large blocks of registers (RAMs or
possibly even register files) but in this design we'll keep it
simple and make everything synchronous.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592