Re: Asgn#3:Clock signal for RAM component

Eugene K Cheung (eugkc@hotmail.com) Fri, 03 Nov 2000 09:30:47 PST 

From: "Eugene K Cheung" <eugkc@hotmail.com>
Subject: Re: Asgn#3:Clock signal for RAM component
Date: Fri, 03 Nov 2000 09:30:47 PST



"Each of the 32x8=256 flip-flops in the RAM is indeed reloaded on
each rising edge of the clock.  The value loaded into each FF is
the same as its current contents unless the write signal is
asserted and the FF is in the byte being addressed.


Why is it necessary to load EACH of the 32 RAM registers on the rise of the 
clock?  Would it not be sufficient to simply reload the specific RAM 
register whose address is incoming (ie: all other registers would be left 
unchanged from the previous cycle, and only one byte can be sent in per 
clock cycle)?

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