Re: EECE 379 Lab 3

Riley Devlin (rileydevlin@hotmail.com) Sun, 29 Oct 2000 00:56:44 PDT 

From: "Riley Devlin" <rileydevlin@hotmail.com>
Subject: Re: EECE 379 Lab 3
Date: Sun, 29 Oct 2000 00:56:44 PDT



Your questions are actually one in the same.  "setting the clock divider to 
2" means that the your circuit should have a 1:2 ratio instead of 
1:25,174,999 ratio.  And you must do this in order to display a change in 
the counter value otherwise the divider output won't be asserted for 
25,175,000 clock cycles(which won't fit on the screen!)  If you read the 
last bullet under "VHDL description" in the lab you should get an idea of 
what is meant by dividing by 2. Hope this helps,

Riley.
>Hello all,
>
>I don't quite understand the following about lab 3:
>
>In page 2, under VHDL description, it says "set the divider value to 2 for 
>testing"????  What is this mean?  I thought the counter suppose to count up 
>or down at 1 Hz.
>
>In addition, I think it is a problem to display the whole waveform since 
>one count up and down period take 1second.  How are we suppose to demo all 
>4 requirement???
>
>Thank you in advance.
>
>Yours truly,
>Edwin Chan

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