EECE 379 Lab 3

Edwin Chan (echan@ece.ubc.ca) Sun, 29 Oct 2000 00:14:47 -0700 

From: "Edwin Chan" <echan@ece.ubc.ca>
Subject: EECE 379 Lab 3
Date: Sun, 29 Oct 2000 00:14:47 -0700




Hello all,

I don't quite understand the following about lab 3:

In page 2, under VHDL description, it says "set the divider value to 2 for testing"????  What is this mean?  I thought the counter suppose to count up or down at 1 Hz.  

In addition, I think it is a problem to display the whole waveform since one count up and down period take 1second.  How are we suppose to demo all 4 requirement???

Thank you in advance.

Yours truly,
Edwin Chan