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MNS Simulation Example

The circuit description is predefined for all IC-CAP configuration files. Enter this description if a new model is being defined; edit the description to fit specific needs. The syntax is identical to the syntax used for describing circuits in a typical MNS simulation deck.

This MNS simulation example will use the IC-CAP supplied Model mnsnpn.mdl.

  1   Select the simulator by choosing Tools > Options > Select Simulator > mns. Choose OK.

  2   Choose File > Open > mnsnpn.mdl. Choose OK.

  3   View the description by clicking the Circuit tab.

The circuit description is shown in the following figure. This deck describes the circuit (in this case, a single device) to be used in the simulation.

Figure 15 MNS Circuit Description Deck for an NPN Bipolar Transistor 
 options ascii=no
model npnbjt bjt NPN=yes \
IS=4.015e-16 BF = 87.01 \
NF = 0.9955 VAF = 84.56 \
IKF = 0.01195 ISE = 3.405E-14 \
NE = 1.594 BR = 10.79 \
NR = 1.002 VAR = 9.759 \
IKR = 0.0237 ISC = 1.095E-15 \
NC = 1.1 RB = 9.117 \
IRB = 0.001613 RBM = 5.62 \
RE = 1.385 RC = 9.292 \
XTB = 1.7 EG = 1.11 \
XTI = 3 CJE = 1.312E-12 \
VJE = 1.11 MJE = 0.3475 \
TF = 5.274E-11 XTF = 5.625 \
VTF = 2.678 ITF = 0.02382 \
PTF = 154.1 CJC = 1.396E-12 \
VJC = 0.4511 MJC = 0.1924 \
XCJC = 0.3 TR = 1E-09 \
CJC = 9.985E-14 VJS = 0.8137 \
MJS = 0.3509 FC = 0.5 
npnbjt:qckt C B E S

  4   To view the input and output for the fearly setup, click the DUTs-Setups tab and select fearly.

The Measure/Simulate folder appears with the inputs vb, vc, ve, and vs, and the output ic. The vc input specifies a voltage source at node C that sweeps linearly from 0 to 5V in 21 steps. The ic output specifies that current at node C be monitored.

In the Plots folder, icvsvc is specified so that the results of the simulation can be viewed graphically.

  5   To simulate, click the Simulate button in the Measure/Simulate folder. The Status line displays Simulate in progress.

When the simulation is complete, the Status line displays IC-CAP Ready.

  6   To view the results of the simulation, display the Plots folder and click Display Plot. The plot displays measured data represented by solid lines and simulated data represented by dashed lines.

Note


Phase information from the sin input cannot be included in the netlist.

Note


For syntax examples of running a remote simulation, refer to "Remote Simulation Examples" in the User's Guide.

The Simulation Debugger

When using MNS with the Simulation Debugger to perform an IC-CAP simulation (as opposed to a manual simulation), an output text file consists of only the computational analysis information. An example of a typical AC analysis output text file is as follows: 

 MNS (ver. 03.00 -- 12 Feb 2004)
Copyright Agilent Technologies, 2004
AC ac1[1] <baaa07774>   freq=(1 kHz->10 MHz)
Time required for ac1[1] was 0.30 seconds.

This file does not include the resulting data. To generate a more informative output text file, change the ascii option in the Input File from ascii=no to ascii=yes and perform a manual simulation. An output text file that includes the simulated output data values is produced. The ascii option is set to no by IC-CAP before every simulation so that the binary raw data file is generated by MNS. IC-CAP needs the binary raw data file to read the resulting simulation data. However, this data is not needed for a manual simulation.

MNS version 4.0 requires that the option nutmeg be set to yes to cause MNS to generate the binary raw data file required by IC-CAP. If the nutmeg option is not specified, the default is nutmeg = yes. If you set nutmeg = no, MNS will generate an output data format that IC-CAP cannot understand.

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