This is what this page is mainly about. My MASc research project is the design and implementation of a soft-core vector processor for the Altera Stratix III FPGA family. The processor uses the Altera Nios II instruction set, plus vector extensions developed by me!
A vector processor is an array of parallel processors that execute the same operation at a time. It is relatively easy to program (just think in vectors like in Matlab programming), and can significantly accelerate applications with data-level parallelism (performing the same operation over alot of data) including embedded applications in image/signal processing, crypto, etc.
The soft vector processor is an effective accelerator for soft-core CPU-based systems on FPGAs. The main benefit is it does not require any hardware design experience or hardware knowledge from the FPGA user to accelerate an application. Instead of designing hardware accelerators in a hardware description language such as VHDL or Verilog, the FPGA user only needs to write vectorized software code to achieve speedup. It provides good performance compared to other easy-to-use solutions such as Altera's C2H (C to hardware) compiler. The soft vector processor is scalable in performance and resource usage, meaning the FPGA user can select the desired performance/area tradeoff when generating the soft vector processor by specifying a few parameters.
See the research page for the latest updates!