netlist_create_from_ast.h File Reference

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Functions
void	create_netlist ()
void	connect_memory_and_alias (ast_node_t *hb_instance, char *instance_name_prefix)

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Function Documentation

void connect_memory_and_alias	(	ast_node_t *	hb_instance,
		char *	instance_name_prefix
	)

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void create_netlist

(

)

Definition at line 129 of file netlist_create_from_ast.c.

{
        /* just build all the fundamental elements, and then hookup with port definitions...every net has a named net as a variable instance...even modules...the only trick with modules will be instance names.  There are a few implied nets as in Muxes for cases, signals for flip-flops and memories */

        /* we will find the top module */
        top_module = find_top_module();
        if (!global_args.output_file)
        {
                global_args.output_file = malloc(strlen(top_module->children[0]->types.identifier) + 5 + 1);
                sprintf(global_args.output_file, "%s.blif", top_module->children[0]->types.identifier);
        }

        /* Since the modules are in a tree, we will bottom up build the netlist.  Essentially, we will go to the leafs of the module tree, build them upwards such that when we search for the nets, we will find them and can hook them up at that point */
        /* PASS 1 - we make all the nets based on registers defined in modules */
        
        /* initialize the string caches that hold the aliasing of module nets and input pins */
        output_nets_sc = sc_new_string_cache();
        input_nets_sc = sc_new_string_cache();
        /* initialize the storage of the top level drivers.  Assigned in create_top_driver_nets */
        verilog_netlist = allocate_netlist();

        /* now recursively parse the modules by going through the tree of modules starting at top */
        create_top_driver_nets(top_module, "top");
        convert_ast_to_netlist_recursing_via_modules(top_module, "top", 0);
        create_top_output_nodes(top_module, "top");

        /* now look for high-level signals */
        look_for_clocks(verilog_netlist); 
}

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