src/base/abci/abcFpga.c File Reference

#include "abc.h"
#include "fpgaInt.h"
Include dependency graph for abcFpga.c:

Go to the source code of this file.

Functions

static Fpga_Man_t * Abc_NtkToFpga (Abc_Ntk_t *pNtk, int fRecovery, float *pSwitching, int fLatchPaths, int fVerbose)
static Abc_Ntk_t * Abc_NtkFromFpga (Fpga_Man_t *pMan, Abc_Ntk_t *pNtk)
static Abc_Obj_t * Abc_NodeFromFpga_rec (Abc_Ntk_t *pNtkNew, Fpga_Node_t *pNodeFpga)
Abc_Ntk_t * Abc_NtkFpga (Abc_Ntk_t *pNtk, float DelayTarget, int fRecovery, int fSwitching, int fLatchPaths, int fVerbose)

Function Documentation

Abc_Obj_t * Abc_NodeFromFpga_rec ( Abc_Ntk_t *  pNtkNew,
Fpga_Node_t *  pNodeFpga 
) [static]

Function*************************************************************

Synopsis [Derive one node after FPGA mapping.]

Description []

SideEffects []

SeeAlso []

Definition at line 248 of file abcFpga.c.

00249 {
00250     Fpga_Cut_t * pCutBest;
00251     Fpga_Node_t ** ppLeaves; 
00252     Abc_Obj_t * pNodeNew;
00253     int i, nLeaves;
00254     assert( !Fpga_IsComplement(pNodeFpga) );
00255     // return if the result if known
00256     pNodeNew = (Abc_Obj_t *)Fpga_NodeReadData0( pNodeFpga );
00257     if ( pNodeNew )
00258         return pNodeNew;
00259     assert( Fpga_NodeIsAnd(pNodeFpga) );
00260     // get the parameters of the best cut
00261     pCutBest = Fpga_NodeReadCutBest( pNodeFpga );
00262     ppLeaves = Fpga_CutReadLeaves( pCutBest );
00263     nLeaves  = Fpga_CutReadLeavesNum( pCutBest ); 
00264     // create a new node 
00265     pNodeNew = Abc_NtkCreateNode( pNtkNew );
00266     for ( i = 0; i < nLeaves; i++ )
00267         Abc_ObjAddFanin( pNodeNew, Abc_NodeFromFpga_rec(pNtkNew, ppLeaves[i]) );
00268     // derive the function of this node
00269     pNodeNew->pData = Fpga_TruthsCutBdd( pNtkNew->pManFunc, pCutBest );   Cudd_Ref( pNodeNew->pData );
00270     Fpga_NodeSetData0( pNodeFpga, (char *)pNodeNew );
00271     return pNodeNew;
00272 }

Abc_Ntk_t* Abc_NtkFpga ( Abc_Ntk_t *  pNtk,
float  DelayTarget,
int  fRecovery,
int  fSwitching,
int  fLatchPaths,
int  fVerbose 
)

FUNCTION DEFINITIONS ///Function*************************************************************

Synopsis [Interface with the FPGA mapping package.]

Description []

SideEffects []

SeeAlso []

Definition at line 47 of file abcFpga.c.

00048 {
00049     int fShowSwitching = 1;
00050     Abc_Ntk_t * pNtkNew;
00051     Fpga_Man_t * pMan;
00052     Vec_Int_t * vSwitching;
00053     float * pSwitching = NULL;
00054 
00055     assert( Abc_NtkIsStrash(pNtk) );
00056 
00057     // print a warning about choice nodes
00058     if ( Abc_NtkGetChoiceNum( pNtk ) )
00059         printf( "Performing FPGA mapping with choices.\n" );
00060 
00061     // compute switching activity
00062     fShowSwitching |= fSwitching;
00063     if ( fShowSwitching )
00064     {
00065         extern Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns );
00066         vSwitching = Sim_NtkComputeSwitching( pNtk, 4096 );
00067         pSwitching = (float *)vSwitching->pArray;
00068     }
00069 
00070     // perform FPGA mapping
00071     pMan = Abc_NtkToFpga( pNtk, fRecovery, pSwitching, fLatchPaths, fVerbose );    
00072     if ( pSwitching ) Vec_IntFree( vSwitching );
00073     if ( pMan == NULL )
00074         return NULL;
00075     Fpga_ManSetSwitching( pMan, fSwitching );
00076     Fpga_ManSetLatchPaths( pMan, fLatchPaths );
00077     Fpga_ManSetLatchNum( pMan, Abc_NtkLatchNum(pNtk) );
00078     Fpga_ManSetDelayTarget( pMan, DelayTarget );
00079     if ( !Fpga_Mapping( pMan ) )
00080     {
00081         Fpga_ManFree( pMan );
00082         return NULL;
00083     }
00084 
00085     // transform the result of mapping into a BDD network
00086     pNtkNew = Abc_NtkFromFpga( pMan, pNtk );
00087     if ( pNtkNew == NULL )
00088         return NULL;
00089     Fpga_ManFree( pMan );
00090 
00091     // make the network minimum base
00092     Abc_NtkMinimumBase( pNtkNew );
00093 
00094     if ( pNtk->pExdc )
00095         pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc );
00096 
00097     // make sure that everything is okay
00098     if ( !Abc_NtkCheck( pNtkNew ) )
00099     {
00100         printf( "Abc_NtkFpga: The network check has failed.\n" );
00101         Abc_NtkDelete( pNtkNew );
00102         return NULL;
00103     }
00104     return pNtkNew;
00105 }

Abc_Ntk_t * Abc_NtkFromFpga ( Fpga_Man_t *  pMan,
Abc_Ntk_t *  pNtk 
) [static]

Function*************************************************************

Synopsis [Creates the mapped network.]

Description []

SideEffects []

SeeAlso []

Definition at line 198 of file abcFpga.c.

00199 {
00200     ProgressBar * pProgress;
00201     Abc_Ntk_t * pNtkNew;
00202     Abc_Obj_t * pNode, * pNodeNew;
00203     int i, nDupGates;
00204     // create the new network
00205     pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD );
00206     // make the mapper point to the new network
00207     Fpga_CutsCleanSign( pMan );
00208     Fpga_ManCleanData0( pMan );
00209     Abc_NtkForEachCi( pNtk, pNode, i )
00210         Fpga_NodeSetData0( Fpga_ManReadInputs(pMan)[i], (char *)pNode->pCopy );
00211     // set the constant node
00212 //    if ( Fpga_NodeReadRefs(Fpga_ManReadConst1(pMan)) > 0 )
00213         Fpga_NodeSetData0( Fpga_ManReadConst1(pMan), (char *)Abc_NtkCreateNodeConst1(pNtkNew) );
00214     // process the nodes in topological order
00215     pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCoNum(pNtk) );
00216     Abc_NtkForEachCo( pNtk, pNode, i )
00217     {
00218         Extra_ProgressBarUpdate( pProgress, i, NULL );
00219         pNodeNew = Abc_NodeFromFpga_rec( pNtkNew, Fpga_ManReadOutputs(pMan)[i] );
00220         assert( !Abc_ObjIsComplement(pNodeNew) );
00221         Abc_ObjFanin0(pNode)->pCopy = pNodeNew;
00222     }
00223     Extra_ProgressBarStop( pProgress );
00224     // finalize the new network
00225     Abc_NtkFinalize( pNtk, pNtkNew );
00226     // remove the constant node if not used
00227     pNodeNew = (Abc_Obj_t *)Fpga_NodeReadData0(Fpga_ManReadConst1(pMan));
00228     if ( Abc_ObjFanoutNum(pNodeNew) == 0 )
00229         Abc_NtkDeleteObj( pNodeNew );
00230     // decouple the PO driver nodes to reduce the number of levels
00231     nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
00232 //    if ( nDupGates && Fpga_ManReadVerbose(pMan) )
00233 //        printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
00234     return pNtkNew;
00235 }

Fpga_Man_t * Abc_NtkToFpga ( Abc_Ntk_t *  pNtk,
int  fRecovery,
float *  pSwitching,
int  fLatchPaths,
int  fVerbose 
) [static]

CFile****************************************************************

FileName [abcFpga.c]

SystemName [ABC: Logic synthesis and verification system.]

PackageName [Network and node package.]

Synopsis [Interface with the FPGA mapping package.]

Author [Alan Mishchenko]

Affiliation [UC Berkeley]

Date [Ver. 1.0. Started - June 20, 2005.]

Revision [

Id
abcFpga.c,v 1.00 2005/06/20 00:00:00 alanmi Exp

] DECLARATIONS ///

Function*************************************************************

Synopsis [Load the network into FPGA manager.]

Description []

SideEffects []

SeeAlso []

Definition at line 118 of file abcFpga.c.

00119 {
00120     Fpga_Man_t * pMan;
00121     ProgressBar * pProgress;
00122     Fpga_Node_t * pNodeFpga;
00123     Vec_Ptr_t * vNodes;
00124     Abc_Obj_t * pNode, * pFanin, * pPrev;
00125     float * pfArrivals;
00126     int i;
00127 
00128     assert( Abc_NtkIsStrash(pNtk) );
00129 
00130     // start the mapping manager and set its parameters
00131     pMan = Fpga_ManCreate( Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), fVerbose );
00132     if ( pMan == NULL )
00133         return NULL;
00134     Fpga_ManSetAreaRecovery( pMan, fRecovery );
00135     Fpga_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
00136     pfArrivals = Abc_NtkGetCiArrivalFloats(pNtk);
00137     if ( fLatchPaths )
00138     {
00139         for ( i = 0; i < Abc_NtkPiNum(pNtk); i++ )
00140             pfArrivals[i] = -FPGA_FLOAT_LARGE;
00141     }
00142     Fpga_ManSetInputArrivals( pMan, pfArrivals );
00143 
00144     // create PIs and remember them in the old nodes
00145     Abc_NtkCleanCopy( pNtk );
00146     Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Fpga_ManReadConst1(pMan);
00147     Abc_NtkForEachCi( pNtk, pNode, i )
00148     {
00149         pNodeFpga = Fpga_ManReadInputs(pMan)[i];
00150         pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
00151         if ( pSwitching )
00152             Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
00153     }
00154 
00155     // load the AIG into the mapper
00156     vNodes = Abc_AigDfs( pNtk, 0, 0 );
00157     pProgress = Extra_ProgressBarStart( stdout, vNodes->nSize );
00158     Vec_PtrForEachEntry( vNodes, pNode, i )
00159     {
00160         Extra_ProgressBarUpdate( pProgress, i, NULL );
00161         // add the node to the mapper
00162         pNodeFpga = Fpga_NodeAnd( pMan, 
00163             Fpga_NotCond( Abc_ObjFanin0(pNode)->pCopy, Abc_ObjFaninC0(pNode) ),
00164             Fpga_NotCond( Abc_ObjFanin1(pNode)->pCopy, Abc_ObjFaninC1(pNode) ) );
00165         assert( pNode->pCopy == NULL );
00166         // remember the node
00167         pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
00168         if ( pSwitching )
00169             Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
00170         // set up the choice node
00171         if ( Abc_AigNodeIsChoice( pNode ) )
00172             for ( pPrev = pNode, pFanin = pNode->pData; pFanin; pPrev = pFanin, pFanin = pFanin->pData )
00173             {
00174                 Fpga_NodeSetNextE( (Fpga_Node_t *)pPrev->pCopy, (Fpga_Node_t *)pFanin->pCopy );
00175                 Fpga_NodeSetRepr( (Fpga_Node_t *)pFanin->pCopy, (Fpga_Node_t *)pNode->pCopy );
00176             }
00177     }
00178     Extra_ProgressBarStop( pProgress );
00179     Vec_PtrFree( vNodes );
00180 
00181     // set the primary outputs without copying the phase
00182     Abc_NtkForEachCo( pNtk, pNode, i )
00183         Fpga_ManReadOutputs(pMan)[i] = (Fpga_Node_t *)Abc_ObjFanin0(pNode)->pCopy;
00184     return pMan;
00185 }

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