This section shows the steps involved in setting up physical testing of the 74LS165 8-Bit Parallel-to-Serial Shift Register. All source files are included so that the reader can download the files and try to setup the test on his or her own. The functional specification of the 74LS165 can be obtained from any TTL databook.
The file ls165.vhd is the VHDL description of the 74LS165. The implementation is very simple and a novice VHDL designer should be able to understand. Synopsys is used to synthesize the VHDL code to a gate-level circuit using the Synopsys' Class library as the target library. The file ls165_gate.vhd is the synthesized circuit that can be used for gate-level simulations. Finally, the file ls165_circuit.ps is the schematic diagram of the synthesized circuit. To perform functional simulation, synthesis, and gate-level simulation with these files, the following Synopsys setup files should be used: .synopsys_dc_setup and .synopsys_vss.setup . These setup files are different from those of the CMC tutorials as a generic technology has been used for the example.
To perform functional and gate-level simulations, the VHDL test benches ls165tb.vhd and ls165tb_gate.vhd are used respectively. Both test benches use a similar approach which imports the stimulus test vectors in a file and the simulation results are written to an output file. The gate-level simulation uses the output file from the functional simulation as input file. This file contains not only the stimulus, but also the expected responses. The gate-level simulation test bench compares the expected responses with actual responses from the circuit and outputs error messages if they do not match.
The functional test vectors are generated with a simple C program ls165tv.c. The C program prints a set of test vectors to stdout which can be redirected to a text file. Each line of the file consists of one vector of stimulus data that the VHDL test bench reads. The test bench uses a clock to output the stimulus data in a periodic manner. Since this is a very simple circuit, there is no expected output included in the test vector generation program. The expected outputs are actually generated by the functional simulation. However, for a more complicated circuit, the expected outputs should be generated and used for functional simulation.
After gate-level simulation, the design can be exported to Cadence to finish the rest of the design flow as described in the Design Flow section. The rest of this section describes the steps on Figure 5 for the 74LS165.
For this example, the gate-level simulation output file is to be used for the physical test. In general, physical testing takes much less time than simulation in Synopsys so a more exhaustive set of test vectors can be used for the physical test. To be able to use the test vectors for physical testing, the test vector file needs to be converted to HP PCF format. This can be done with a C program or with a Perl script. For the 74LS165, the Perl script topcf.pl (use the right mouse button to download file) is used to convert the gate-level simulation output file to PCF format which can be imported into the HP Test Development Software.
The remaining steps involve creating the SCPI commands to load into the D20 hardware with the HP E1496A Test Development Software, entering the hardware pin assignments in the CMC VXI Test Fixturing Software, and development a test program in VEE test. The output file from the Test Fixturing Software can be used to make the jumper connections on the test head and to connect the timing and pattern pods from the VXI mainframe to the test head. Since the CMC digital tutorial contains a step by step procedure of how to use the Test Fixturing Software, a description will not be given here. The file ls165.vxi is the Test Fixturing Software source file for the 74LS165 and the file ls165.ps is the output file which shows all the jumper and pod connections.
The following subsections describe the use of the HP Test Development Software and VEE Test for this example:
