Amir Masnadi, PhD

Senior Staff RFIC, Analog & Mixed-Signal Designer
Maxlinear Technology
Working on Ultra-High-Speed Wireline Datalinks (28-200 GB/s) - 5-16nm FinFet
Address:  4370 Still Creek Dr suite

Research Interest:

    •Ultra Low Power Wireless - Battary-Less Wireless
    •Ultra High Speed Wireline
   • Fundamental Limits of CMOS Electronics
   • 60GHz to Terahertz Electronics
   • Communication Circuits, Low Power , Low Voltage
   • CDR Systems
   • High Speed Transceiver for Optical Communication
   • Radar System


*************************************  Links *************************************
Link to Linkedin 
Link to my Google Scholar      UBC News

Cool stuff and some of previous projects :
Voyager Mission Operations Status Report
Link to Signal Path       
Understand Complex Things Easy

Privious Projects :
Link to Maktabkhooneh 
Link to Takhte-Sefid

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Hello World !!  My name is Amir Masnadi, I received my MSc. and PhD. with honors from System on Chip Laboratory, University of British Columbia, Canada. I am thrilled to be recipient of Canada Vanier Scholarship and Killam Fellowship during my PhD. 
I received my BSc. as a first rank student from University of Tehran, Iran.




A.H Masnadi Shirazi, S.Mirabbasi "An Ultra-Low-Voltage CMOS Mixer Using Switched-Transconductance, Current-Reuse and Dynamic-Threshold-Voltage Gain-Boosting Techniques", Paper Accepted, NEWCAS, 10th IEEE International, 2012,

            Abstract- The scaling of CMOS technologies has a great impact on analog and radio-frequency (RF) circuit design. In particular, as technology advances the available voltage headroom is decreased due to the use of lower supply voltage. In this paper, an architecture for ultra-low-voltage RF CMOS mixers is introduced. The structure uses switched- transconductance technique in conjunction with current-reuse and dynamic-threshold-voltage gain-boosting techniques to reduce the required supply voltage and power consumption while providing a high conversion gain. As a proof-of-concept, a 2.5-GHz down-conversion mixer is designed and laid out in a 0.13-m CMOS process. Post-layout simulation results show that the mixer achieves a conversion gain of 13 dB while consuming 480 W from a 0.35-V supply.













        








•   H. Rashtian, A.H Masnadi Shirazi, S.Mirabbasi On the Use of  Body-Biasing to Improve Linearity in Gilbert-Cell CMOS Mixers", Paper Submitted, MWSCAS 2012.

            Abstract-this paper presents the application of body-biasing to improve linearity performance of Gilbert-cell CMOS mixers. In order to improve the linearity, the bulk bias voltage of the transistors in the local oscillator (LO) stage is adjusted. Based on post-layout simulation results, this technique results in a 5 dB improvement in the third-order intercept point (IP3) of the mixer. The improvement in linearity is obtained while the conversion gain and power consumption of the mixer remain virtually intact. A 0.13-m CMOS proof-of-concept prototype is implemented which operates at radio frequency (RF) of 2.4 GHz with an intermediate frequency (IF) of 50 MHz and draws 2.25 mA from a 1.2 V supply.
















 






• A.H Masnadi Shirazi, Hooman Rashtian ,S.Mirabbasi A Linearity Enhancement Technique and Its Application to CMOS Wideband Low-Noise Amplifiers  ", ICECS, 2012,

            Abstract-Undesired harmonics have severe impacts on performance of electronic circuits and systems, especially for those used for radio frequency (RF) applications. In this paper, a harmonic cancellation technique based on combining two phase-shifted versions of the signal is introduced. As a proof-of-concept, a wideband (0.07 to 7.5 GHz) low-noise amplifier (LNA) with 3rd-harmonic cancellation technique is designed and laid out in a 0.13-m CMOS process. In this design, phase-shifter circuits are implemented using passive lumped components. Post-layout simulation results show that the LNA achieves a noise figure (NF) of 2.3 dB, S21 of 17.9 dB while consuming 15.6 mW from a 1.2 V supply and significantly cancelling the 3rd harmonic.











Selected Publication : Link to my Google Scholar
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   • A.H Masnadi Shirazi, "Ab initio Absorption Study of Water and Oxygen Mixture; IR and Millimeter Waves", UBC, 2012, PDF

            Abstract: Optical absorption of water and oxygen molecules plays an important role in total absorption of ambient atmosphere. In this work, first the principle of optical absorption is discussed, and then absorption spectrum of each molecule at different phases (single molecule, liquid and gas) is studied using density function theory, Hartree-Fock and Molecular Dynamics methods. Finally, mixture of oxygen and water with their atmospheric proportions is made and studied. It is found that the oxygen absorption is dominant in the range of 1000-2000 cm-1, while water absorption is governing in vast range of millimeter waves and terahertz (main absorber of sun light). In addition, it is shown that pressure of mixture can change the vibration modes and absorption spectrum respectively.














Useful Software :
              
ADF: Amsterdam Density Functional software
Our two flagship Density Functional Theory (DFT) programs are powerful computational tools to understand and predict chemical structure, reactivity, and spectroscopy:

•ADF for molecules
•BAND for periodic systems

Our programs run in parallel out-of-the-box on Windows, Mac, and Linux, with an excellent Graphical User Interface. ADF and BAND feature relativistic effects and localized Slater basis sets for the entire periodic table, with a strong track record in tackling challenging chemical problems, in particular:

•spectroscopy
•structure and reactivity
•chemical analysis
•transition metals and heavy elements
•environment effects (solvents, proteins)

We also offer quick, more approximate methods for studies in chemistry, chemical engineering, and material science:

•DFTB: fast approximate DFT
•MOPAC2009: semi-empirical code
•ReaxFF: reactive force field dynamics
•COSMO-RS: fluid thermodynamics

Our highly trained team of theoretical chemists and physicists continue to expand the scope and functionality of our software and offer full scientific support. Included tools enable QM/MM, ONIOM, adaptive MD, and meta-dynamics.



BSc. Reports
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• A.H Masnadi Shirazi, "Ab initio Study of Hydrogen Molecule", UBC, 2012, PDF , Matlab Code

                                               
                In this work Hydrogen molecule is solved by HF method. Matlab code is available

• A.H Masnadi Shirazi, "On Design of CIGS-Metal Solar Cell - Challenges and Optimization", UBC, 2011, PDF




• A.H Masnadi Shirazi, "Design of AlGaInP Orange LED and a study on Dichoromic and Trichromic White LED", UBC, 2011, PDF





A.H Masnadi Shirazi, Parisa Owji, Error Concealment In Image Communication Using Edge Map Watermarking and Spatial Smoothing, Electrical Engineering Department, University of Tehran, 2009.

                  Abstract: We propose a simple and efficient method for reconstructing an image which passed from network tunnel in transmitter and because of AWGN error some of its information missed in receiver. We use edge map, watermarking and estimation to predict what the losses are.











A.H Masnadi Shirazi, S.Mirabbasi "An ultra-low-voltage ultra-low-power CMOS active mixer", Journal of Analog Integrated Circuit and Signal Processing, Springer, 2013Link , PDF

            Abstract: The scaling of CMOS technology has greatly influenced the design of analog and radio frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption that is capable of operating from a supply voltage comparable or lower than the threshold voltage of the transistor. In addition, the proposed architecture provides a performance and conversion gain (CG) that compares favorably or exceeds those of the state-ofthe- art designs. As a proof-of-concept, a wide-band DC to 8.5 GHz down-conversion mixer is designed and fabricated in a 90-nm CMOS process. Measurement results show that the mixer achieves a CG as high as 18 dB while consuming 98 lW from a 0.3-V supply.












        


A.H Masnadi Shirazi, S.Mirabbasi "A low-power 2.4-GHz combined LNA-VCO structure in 0.13-
m CMOS", Journal of Analog Integrated Circuit and Signal Processing, Springer, 2013, Link , PDF

            Abstract: A combined low-noise amplifier and voltage-controlled oscillator (LNA-VCO) is designed and laid-out in a 0.13-
m CMOS technology. The low-power LC VCO and LNA circuits are stacked and share the same bias current. An LC filter is used between the LNA and the VCO to improve the phase noise performance of the VCO. Based on post-layout simulations, the LNA achieves a gain of 17.7 dB and a noise figure of 5.1 dB at 2.4 GHz. The VCO has a center frequency of 2.45 GHz with a 370 mV output swing and a phase noise of -111 dBc/Hz at 1-MHz offset. The LNA-VCO consumes 124 W from a 0.8 V supply.












        
Recently Submitted Thesis :
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Title: On the design of low-voltage power-efficient CMOS active down-conversion mixers
Author: Masnadi Shirazi Nejad, Amir Hossein
Degree: Master of Applied Science - MASc
Program: Electrical and Computer Engineering
Copyright Date: 2013
Publicly Available in cIRcle: 2013-04-12
Click Here for This Thesis

Abstract: The scaling of CMOS technologies has a great impact on analog and radio-frequency (RF) circuit design. In particular, as technology advances the available voltage headroom is decreased due to the use of lower supply voltage. In addition to design challenges due to the headroom limitation, the power consumption is also becoming more important, in particular, in wireless communication applications and portable devices. In this work, we investigate several design techniques for achieving ultra-low-voltage (< 0.5 V), ultra-low-power (< 500 W), and ultra-wideband (DC to 8 GHz) wireless receiver building blocks with a specific focus on the active CMOS mixers. Mixers are important building blocks of almost all modern transceivers and they are primarily used for frequency translation.

In this work, we briefly review many state-of-the-art design techniques, discuss the advantages and drawbacks of currently used methods, and then we introduce design techniques to improve performances of different receiver building blocks, namely, mixers and LNAs. As a proof-of-concept three different RF active CMOS mixers are designed, have been fabricated in 0.13-m and 90-nm CMOS processes, and are successfully tested. We have also proposed a linearization method, which is specifically applicable to mixers and low-noise-amplifiers (LNAs). A proof-of-concept circuit for the proposed linearization technique is also designed and implemented in a 0.13-m CMOS process and is successfully tested.


A.H Masnadi; Nikpaik, Amir; Molavi, Reza; Mirabbasi, Shahriar; Shekhar, Sudip, "A Class-C self-mixing-VCO architecture with high tuning-range and low phase-noise for mm-wave applications," in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, vol., no., pp.107-110, 17-19 May 2015  Link , PDF

            Abstract: Achieving high tuning-range and low phase-noise simultaneously in mm-wave voltage-controlled oscillators (VCO) has been a severe design challenge. Our architecture, referred herein as a self-mixing VCO (SMV), utilizes a Class-C push-push VCO topology to generate the first (f0) and second harmonics (2f0) and then mixes them together to obtain the desired third harmonic (3f0) component. Compared to a fundamental-mode VCO operating at 3f0 in mm-wave band, the SMV architecture achieves superior frequency tuning range (FTR) and phase-noise (PN) performance. A Class-C topology enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance and reduces phase noise. A 52.8-to-62.5 GHz SMV prototype is designed and implemented in a 0.13-m CMOS process. Measurement results show an FTR of 16.8% together with a PN of
-100.57 dBc/Hz at 1 MHz offset - resulting in an FTR-inclusive figure-of-merit (FOMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply voltage.        




Nikpaik, A.; Nabavi, A.; Shirazi, A.H.M.; Shekhar, S.; Mirabbasi, S., "A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoM," in IEEE Custom Integrated Circuits Conference (CICC), 2015 , vol., no., pp.1-4, 28-30 Sept. 2015 Link , PDF

            Abstract: There exists a fundamental limit in improving the phase noise performance of LC-tank oscillators. Impediments to reach this limit are first discussed, and then a clipping LC VCO topology based on dual tank is presented to mitigate them. This topology can approach within 3 dB of the maximum thermodynamically achievable figure-of-merit (FoM) limit. Compared to conventional class-B/C/D/F oscillators, it is capable of reducing both close-in and far-out phase noise. As a proof of concept, a prototype 4.17-4.95 GHz VCO in a 0.13-
m CMOS process achieves a phase noise of -97 and -143 dBc/Hz at 30 kHz and 3 MHz offset, respectively.        

Title: Radio frequency CMOS : from ultra-high speed to ultra-low power
Author: Amir Masnadi
Degree: Doctor of Philosophy - PhD
Program: Electrical and Computer Engineering
Copyright Date: 2018
Click Here for This Thesis

Abstract: Over the last three decades, radio-frequency(RF) Complementary Metal-Oxide-Semiconductor(CMOS) electronics has made a huge impact in our world. Wireless Local Area Networks(WLANs), cellular networks, Global Positioning Systems(GPSs), and Bluetooth are a few examples where the impact of RF CMOS has led to rapid adoption and standardization of the technology. However, there still exists several challenging areas at the intersection of RF and CMOS where new paradigms must be established. This thesis summarizes the research to meet those goals as briefly described here: Research during the past decades provided CMOS solutions to RF applications that utilize the frequency spectrum up to 6 GHz. However, efficient system integration of mm-wave and THz in CMOS is still a challenging task. The THz spectrum is gaining interest due to its wider and less populated available spectrum, as well as its intriguing applications in molecular spectroscopy, imaging, and sensing. This band, although very useful, has been difficult to realize in hardware because of the limitations in CMOS electronics. In the first four chapters of this thesis, we investigate the challenge of implementing signal-sources at mm-wave and sub-THz frequencies using low-cost and versatile CMOS circuits, replacing the existing expensive solutions. Demand for embedded low-power electronics for wireless connectivity is growing due to the rapid proliferation of Internet-of-Things (IoT). Although Wireless Sensor Network(WSN) had been around for decades, some applications such as biomedical monitoring systems require ultra-low-power(ULP) and cost-effective wireless solutions. Research on energy-harvesting systems (e.g., RF energy harvesting, thermoelectric, etc.) and integrated-circuits(IC) bears the promise of medium-reach battery-free wireless connectivity solutions. In Chapters 5 and 6 of this thesis, multiple ULP wireless connectivity solutions for both commercial standards such as Bluetooth Low Energy(BLE) and custom-designed application-specific-radios are proposed and implemented in 40nm and 130nm CMOS technologies, respectively. Finally, application of RF electronics in power-electronics is studied in the last chapter. Although power-management integrated circuit is a well-developed field of research, PMICs still have existing bottlenecks (e.g., die area and output ripple) which can be addressed with the knowledge of RF electronics. In this thesis, feasibility of GHz-range converters is studied.


A. Masnadi et al., "A Compact Dual-Core 26.1-to-29.9GHz Coupled-CMOS LC-VCO with Implicit Common-Mode Resonance and FoM of-191 dBc/Hz at 10MHz," 2020 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2020, pp. 1-4, PDF

A compact dual-core, single-transformer, and low-power voltage-controlled oscillator (VCO) is presented. The single transformer provides resonance at both differential and common modes, eliminating the need for an explicit inductor for the common-mode resonance. It is implemented vertically using two top metal layers, resulting in significant area saving compared to the state-of-the-art. The LC-tank has common mode resonance at twice the VCO frequency, hence reducing the flicker noise corner frequency of the VCO to 450 kHz. A fully-balanced complementary coupled-Class-C design improves efficiency, maintains symmetric swings across the transformer, and improves reliability. A prototype 26.1-to-29.9 GHz VCO, suitable for 5G applications, is implemented in a 65-nm CMOS process occupying an area of 0.04 mm2 . The VCO consumes 3.4 mW at 27.45 GHz and exhibits a phase noise of 127.5 dBc/Hz at 10 MHz offset resulting in an FoM of
-191 dB/Hz.



A quad-core-coupled triple-push 295-to-301 GHz source with 1.25 mW peak output power in 65nm CMOS using slow-wave effect PDF

Achieving high output power in (sub-)THz voltage-controlled oscillators (VCOs) has been a severe design challenge in CMOS technology. In this work, an architecture for coupled terahertz (THz) VCOs is presented. The architecture utilizes four coupled triple-push VCOs and combines the generated third harmonic currents using slowwave coplanar waveguide (S-CPW) at 300 GHz. Coupling four cores increases output power, and use of S-CPW reduces the loss and increases the quality factor of the VCO tank. It is shown that using S-CPW results in ~2.6 dB of lower loss as compared to the conventional CPW or grounded-CPW (GCPW) structures. The VCO is tuned using parasitic tuning technique and achieves 1.7% frequency tuning range (FTR). The proposed structure is designed and fabricated in a 65-nm bulk CMOS process. The measured peak output power of the 295-to-301 GHz VCO is 0.9 dBm (
1.25 mW) at 300 GHz while consuming 235 mW (with a DC to RF efficiency of 0.52%). Index Terms CMOS, coup



A. H. Masnadi Shirazi et al., "On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise," in IEEE Journal of Solid-State Circuits, vol. 51, no. 5, pp. 1210-1222, May 2016 PDF

Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first (f?) and second harmonic (2f?) and then mixes them together to obtain the desired mm-wave third-harmonic (3f?). Use of a Class-C push-push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance, and improves PN. Compared to an F-VCO operating in a mm-wave band at a fundamental frequency that equals 3f?, the proposed SMV architecture achieves about 2 higher FTR and a better PN performance. A 52.8-62.5 GHz SMV prototype is designed and implemented in a 0.13 m CMOS process. Measurement results show that the VCO achieves an FTR of 16.8% with a PN of -100.6 dBc/Hz at 1 MHz offset-resulting in an FTR-inclusive figure-of-merit (FoMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply.



A. Nikpaik, A. H. Masnadi Shirazi, A. Nabavi, S. Mirabbasi and S. Shekhar, "A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 53, no. 2, pp. 389-403, Feb. 2018, doi:PDF

Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively.


A. H. M. Shirazi, H. M. Lavasani, M. Sharifzadeh, Y. Rajavi, S. Mirabbasi and M. Taghivand, "A 980W 5.2dB-NF current-reused direct-conversion bluetooth-low-energy receiver in 40nm CMOS," 2017 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, 2017, pp. 1-4, doi:PDF

A compact dual-core, single-transformer, and low-power voltage-controlled oscillator (VCO) is presented. The single transformer provides resonance at both differential and common modes, eliminating the need for an explicit inductor for the common-mode resonance. It is implemented vertically using two top metal layers, resulting in significant area saving compared to the state-of-the-art. The LC-tank has common mode resonance at twice the VCO frequency, hence reducing the flicker noise corner frequency of the VCO to 450 kHz. A fully-balanced complementary coupled-Class-C design improves efficiency, maintains symmetric swings across the transformer, and improves reliability. A prototype 26.1-to-29.9 GHz VCO, suitable for 5G applications, is implemented in a 65-nm CMOS process occupying an area of 0.04 mm2 . The VCO consumes 3.4 mW at 27.45 GHz and exhibits a phase noise of 127.5 dBc/Hz at 10 MHz offset resulting in an FoM of
-191 dB/Hz.

M. Sharifzadeh, A. H. Masnadi-Shirazi, Y. Rajavi, H. M. Lavasani and M. Taghivand, "A fully integrated multi-mode high-efficiency transmitter for IoT applications in 40nm CMOS," 2018 IEEE Custom Integrated Circuits Conference (CICC), San Diego, CA, 2018, pp. 1-4, doi:
PDF

This paper presents a fully integrated multi-mode high efficiency transmitter (TX), employing supply scaling technique using a DC-DC converter to improve the efficiency for low power body area network (BAN) applications while supporting higher power Bluetooth Low Energy (BLE) applications. The proposed architecture improves the efficiency of the conventional constant-supply switching PAs by a factor of 3 in low power mode, resulting in power saving of nearly 1mW at -10dBm output power. The TX benefits from a compact 0.1mm 2 PLL operating with an IPN of 0.83 at 2.4GHz and spot phase noise of -119.4dBc/Hz at 3MHz offset. The chip is fabricated in a 40nm LP CMOS process with a die area of 0.7mm 2 . The proposed transmitter consumes 6.1mW at 3dBm output power in BLE mode and 1.6mW at -10dBm for BAN applications, which is, to the best of our knowledge, the lowest reported power consumption among the BLE transmitters in similar process node.






A. El Sayed et al., "A Hilbert Transform Equalizer Enabling 80 MHz RF Self-Interference Cancellation for Full-Duplex Receivers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, :PDF

A passive, time-domain equalizer is presented that achieves a broadband self-interference cancellation (SIC) over 80 MHz of RF bandwidth for simultaneous full-duplex radios. A baseband Hilbert transform technique reduces the number of equalizer taps needed for SIC, and with frequency translations, results in an equivalent RF-domain equalization. A proof-of-concept prototype in 0.13-m CMOS process attains a measured 23 dB of SIC over an 80 MHz signal bandwidth at 900 MHz, and consumes 13 mW of clocking power independent of SIC equalizer settings. Its impact on the receiver noise figure is 1.4 dB. The equalizer and the receiver together consume 64.4 mW from a 1.2 V supply in an active area of 0.72 mm 2


Hobbies

    •Investment - Portfolio Analysis
    •Fine Woodworking
    •Gardening       
   • Baking Different Kinds of Bread
   • RC-FPV Drone/Plane
   • Hiking