prev FPGA 2002 done!
Summary

  1. level restoring
    • improves static power, raises new problem
  2. tile length
    • one buffer size adequate, simplifies research
  3. buffer construction
    • 3 stages, sense low-voltage input
  4. intrinsic buffer delay depends on input slew rate
    • 10% of delay: routing can ignore, timing analyzer should estimate
  5. best switch sizes: 0.18um similar to 0.35um
    • size 6 buffer, size 10 pass transistor (we used 16)
  6. fanin switches useful
    • bufm saves 7% delay, and 3% area
  7. buffer/pass switching
    • save over 10% area, area*delay
    • difficult to realize delay improvement (10% potential)
      • note: would be impossible without bufm
    • still need purely-buffered interconnect for high fanout nets?