#include <vpr_types.h>

Detailed Description

Defines the detailed routing architecture of the FPGA. Only important if the route_type is DETAILED.

directionality: Should the tracks be uni-directional or bi-directional? (UDSD by AY)
Fc_type: Are the Fc values below absolute numbers, or fractions of W?
Fc_output: Number of tracks to which each clb output pin connect in each channel to which it is adjacent.
Fc_input: Number of tracks to which each clb input pin connects.
Fc_pad: Number of tracks to which each I/O pad connects.
switch_block_type: Pattern of switches at each switch block. I assume Fs is always 3. If the type is SUBSET, I use a Xilinx-like switch block where track i in one channel always connects to track i in other channels. If type is WILTON, I use a switch block where track i does not always connect to track i in other channels. See Steve Wilton, Phd Thesis, University of Toronto, 1996. The UNIVERSAL switch block is from Y. W. Chang et al, TODAES, Jan. 1996, pp. 80 - 101.
num_segment: Number of distinct segment types in the FPGA.
num_switch: Number of distinct switch types (pass transistors or buffers) in the FPGA.
delayless_switch: Index of a zero delay switch (used to connect things that should have no delay).
wire_to_ipin_switch: Index of a switch used to connect wire segments to clb or pad input pins (IPINs).
R_minW_nmos: Resistance (in Ohms) of a minimum width nmos transistor. Used only in the FPGA area model.
R_minW_pmos: Resistance (in Ohms) of a minimum width pmos transistor.