df/dac/globals__declare_8h_source.html

00001 /**@{*/
00002 /** Netlist to be placed stuff. */
00003 int num_nets, num_blocks;
00004 struct s_net *net;
00005 struct s_block *block;
00006 boolean *is_global;
00007 /**@}*/
00008
00009 /** Physical FPGA architecture stuff */
00010 int nx, ny;
00011
00012 /**@{*/
00013 /** chan_width_x is the x-directed channel; i.e. between rows */
00014 int *chan_width_x, *chan_width_y;       /**< numerical form */
00015 struct s_grid_tile **grid;
00016 /**@}*/
00017
00018 /** [0..num_nets-1] of linked list start pointers.  Defines the routing.  */
00019 struct s_trace **trace_head, **trace_tail;
00020
00021 /**@{*/
00022 /** Structures to define the routing architecture of the FPGA.           */
00023 int num_rr_nodes;
00024 t_rr_node *rr_node;             /**< [0..num_rr_nodes-1]          */
00025 t_ivec ***rr_node_indices;
00026 int num_rr_indexed_data;
00027 t_rr_indexed_data *rr_indexed_data;     /**< [0 .. num_rr_indexed_data-1] */
00028 int **net_rr_terminals;         /**< [0..num_nets-1][0..num_pins-1] */
00029 struct s_switch_inf *switch_inf;        /**< [0..det_routing_arch.num_switch-1] */
00030 int **rr_blk_source;            /**< [0..num_blocks-1][0..num_class-1] */
00031 /**@}*/