problem solving in the lab

Ed Casas (edc@ece.ubc.ca) Sat, 13 Feb 1999 15:54:57 -0800 

Date: Sat, 13 Feb 1999 15:54:57 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: problem solving in the lab



> I'm a student in your Elec 379.  I'm the one who couldn't
> finish Lab 3 on time, but so did many others.  On thursday when
> the lab time is up at 11:30, only ONE student finished the lab.
> The TA himself said that 3 hours is not enough for this lab.

Rob told me that those students that were prepared for the lab
were able to finish in 15 minutes.

> I left at 11:30 since there were students from the next session
> coming in, and they didn't have computer to work on.  But the
> others stayed and continued working on their lab, which means
> they had extra time and some of them managed to finish the lab.
> To my point of view, this is unfair.

It *would* be most unfair.  Students who did not finish on time
will not get marks for completing the lab.

> Q: what could be the problem if my program shows many zeros?
> Is it the problem of my VHDL code?

The purpose of the lab part of the course is to learn how to
solve problems like this efficiently.

The general approach is:

- based on your understanding of the system you're
designing/testing, guess at a possible cause

- come up with a way to test your guess

- repeat the previous two steps until the problem is solved

To do this efficiently you have to understand how things ``work''
(VHDL models and CPU instructions in this case), be able to
reason (relate cause and effect) and be able to use test
equipment (logic analyzer).

As an exercise, make as long a list as possible of reasons why
your program is printing zeros and a way that you could rule out
each cause.  You should be able to come up with a dozen or more
possible reasons.  Then see if you can figure out any tests that
would rule out several of these possible causes.  Then rank the
tests in the order which you think will identify the cause of
your problem most quickly.  The do the tests one by one until you
find the problem.  Some test results may lead you to make other
hypothesis and further measurements.  Use your imagination and
persevere.

You should be able to do some (most) of these tests on your own
by modifying and running your assembly language program and
simulating your VHDL code.

Let me know if this doesn't resolve your problem.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592