Re: CUPL simulator

Ed Casas (edc@ece.ubc.ca) Mon, 13 Nov 2000 14:57:03 -0800 

Date: Mon, 13 Nov 2000 14:57:03 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: CUPL simulator



> I'm having trouble using the CUPL simulator to test my logic
> equations.  My logic equations are of the form y=fn(x,y) such
> that the state variable 'y' is a function of its previous value
> and some other variables.  However, the simulator does not seem
> to be able to distinguish between a state variable as an input
> and an output in the vector.  To define the vectors H/L are
> used for outputs and 1/0 are used for inputs.  but when I have
> a state variable as a vector input, it requires me to define
> those state variables using H/L.  Thus the simulator appears to
> generate errors that are caused by the duplicate (as seen by
> the complier) set of expected output values in a vector.

You can only specify the values on the input pins (clock,
switches) as test vector inputs.  The state variables appear on
output pins, so you shouldn't specify them as inputs.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592