Re: Fw: Assignment #4

Ed Casas (edc@ece.ubc.ca) Sun, 10 Dec 2000 19:54:01 -0800 

Date: Sun, 10 Dec 2000 19:54:01 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Fw: Assignment #4



> For signal tRC of SRAM read cycle, tWC of SRAM write cycle, and
> tRC of flash read cycle, their expressions of guaranteed
> responses are all 4C (160ns) as stated on the solution
> handout. Does this mean that the microprocessor is always
> reading for a certain CPU cycle and writing for the next CPU
> cycle? Couldn't the microprocessor read or write for more than
> 2 consecutives cycles instead?

Yes, but presumably the reads or writes would be to different
addresses and so they would be different cycles.

> Also, it looks to me that the width of a signal on the address
> bus equals to t41+t46+t42 (all of these three are guaranteed
> responses) on figure 17 of the Intel386EX datasheet. Again, why
> signals tRC of SRAM read cycle, tWC of SRAM write cycle, and
> tRC of flash read cycle all have expressions 4C (160ns), but
> not t41+t46+t42 (70ns)?

The convention used on timing diagrams to indicate the cycle time
is somewhat confusing (I pointed this out in class).

Although the cycle time is drawn on the timing diagram as the
time between address changes, it is really the bus cycle period
and could be drawn between any two instances of the same
transition on successive cycles.  Manufacturers use the address
bus to mark the cycle time because it's the most convenient
signal: it's usually the first signal to go valid.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592