Re: Asgn#3:Clock signal for RAM component

Ed Casas (edc@ece.ubc.ca) Fri, 3 Nov 2000 04:38:07 -0800 

Date: Fri, 3 Nov 2000 04:38:07 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Asgn#3:Clock signal for RAM component



> For the RAM component in assignment 3 the clock that
> drives the CPU also must drive the RAM. However, I am
> uncertain as to the purpose of this. If on every
> rising clock edge data is read or writtin to the RAM
> (depending on the read/write signal) then how do we
> instruct the RAM to sit idle when needed? i.e not to
> read or write from memory, regardless of the
> read/write signal. 

Each of the 32x8=256 flip-flops in the RAM is indeed reloaded on
each rising edge of the clock.  The value loaded into each FF is
the same as its current contents unless the write signal is
asserted and the FF is in the byte being addressed.

This synchronous arrangement is reasonable for a small memory (a
``register file'') like this.  Larger memories would certainly
use a different structure that was more power- and
space-efficient.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592