Re: lab 3

Edwin Chan (echan@ece.ubc.ca) Sun, 29 Oct 2000 20:58:32 -0800 

From: "Edwin Chan" <echan@ece.ubc.ca>
Subject: Re: lab 3
Date: Sun, 29 Oct 2000 20:58:32 -0800




The clock divider circuit is a counter that counts from 0 to 25,174,999 (the clock frequency - 1) and then starts at 0 again. Everytime when the countering state is 0, you generate a pulse.

----- Original Message ----- 
From: Ivan Sun 
To: eece379@fs3.ece.ubc.ca 
Sent: Sunday, October 29, 2000 6:34 PM
Subject: lab3


Hi 
I have a question about the clock divider. How could we convert the input clock frequency to 1 Hz output? I have already calculated the number of bits required for the counter state. Could someone help this?

Thanks,
Ivan