Re: Question about Assignment 1

Ed Casas (edc@ece.ubc.ca) Sat, 14 Oct 2000 06:54:26 -0700 

Date: Sat, 14 Oct 2000 06:54:26 -0700
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Question about Assignment 1



> I have two questions about assignment 1:

> 1) The datasheet state that "if loaded witha code in excess of
> 9 they return to their legitimate squence within two counts".
> Do we have to make this "delay" to our VHDL code? or we just
> set the counter to 4 on the next count immediately.

"Within two counts" includes the cases where the transition to a
value between 0 and 9 takes 0, 1 or 2 counts (see the state
transition diagram on page 2).

> 2) I don't really understand test case #4. I think when the
> current state is 9, the next state is 0 (not 5).

Yes, this is not clearly stated.  The intent is that you should
test the sequence 5,6,...,9,0,1,...,5.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592