Re: EECE379 Lab1

Ed Casas (edc@ece.ubc.ca) Mon, 18 Sep 2000 07:14:16 -0700 

Date: Mon, 18 Sep 2000 07:14:16 -0700
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: EECE379 Lab1



> Just would like to verify with you, for lab1 do we need to
> design the sequential circuit or we only need to write the VHDL
> source code?

You do have to design the circuit, but not at the gate level.
The lab instructions say you have to submit a block diagram (see
course Web page for more details) and the corresponding VHDL
code.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592