Re: eece379 Lab1

Ed Casas (edc@ece.ubc.ca) Sun, 17 Sep 2000 13:03:17 -0700 

Date: Sun, 17 Sep 2000 13:03:17 -0700
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: eece379 Lab1



> I really don't know how to write the VHDL code for Lab1. Can
> you give me a outline (or hint) of writing the code?

Here's some hints based on the experiences of students in
previous labs:

The circuit is a state machine.

Read and follow the step-by-step instructions for designing a
state machine given in the notes.

Use bit_vectors and selected assignments (not sum-of-product
expressions) to implement the combinational logic.  Generating
the sum-of-products expressions will work, but it is error-prone,
will take you much longer and will be difficult to debug in the
lab.

There are two possible state encodings: the 7-segment outputs or
the binary representation of the count.  Either way will work.

[If you've been able to work out both approaches, think about the
following: Which one appears to be more efficient?  Which one is
easier to understand and debug?  Which of these two
considerations is most important for this lab?]

You need to use the reset input as well as the current state in
the combinational logic that determines the next state.  There
are two ways to do this:

(1) combine the reset input with the current state into a new
signal and use the whole thing as the input to the combinational
logic block (define a new signal within the architecture, use the
VHDL '&' operator to concatenate the current state and the reset
signal and use the new signal as the select expression).

(2) break the problem into two sub-problems (two logic blocks):
The first block computes the next state as a function of the
current state assuming the reset input is not asserted.  The
second block computes the next state based on the reset input and
the output of the first block.  Again, you'll have to define an
extra signal within the architecture.

[Again, if you can see how both approaches would work, which one
would be a better solution for this lab?]

Get the details right! (Or it won't work and you may not have
enough time to figure it out in the lab).  Are the inputs
active-high or active-low?  How about the outputs?  Which LED
segment is connected to which FPGA pin?

DO NOT FOLLOW THE STATE MACHINE EXAMPLES IN THE MAXPLUSII
DOCUMENTATION!  (as explained in the notes, in this course you
are not allowed to generate combinational logic using a process
statement).

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592