Changes to Lab 4

Ed Casas (edc@ece.ubc.ca) Wed, 8 Mar 2000 10:36:45 -0800 

Date: Wed, 8 Mar 2000 10:36:45 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Changes to Lab 4



Those students that still have not done Lab 4 should change their
designs to use the 25.175 MHz "osc" signal that is permanently
connected to FPGA pin 91 instead of the 8.333 MHz PC-104 bus
signal "sysclk" which is normally connected to pin 211 via the
prototyping board.

You'll also need to increase the clock divider by a factor of
about 3 (and possibly increase the number of bits in the clock
divider).

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592