Architectural Support for Block Transfers in a Shared-Memory Multiprocessor

Steven J.E. Wilton and Zvonko G. Vranesic
Department of Electrical and Computer Engineering
University of Toronto
Toronto, Ontario, Canada, M5S 3G4

Abstract:

This paper examines how the performance of a shared-memory multiprocessor can be improved by including hardware support for block transfers. A system similar to the Hector multiprocessor developed at the University of Toronto is used as a base architecture. It is shown that such hardware support can improve the performance of initialization code by as much as 50%, but that the amount of improvement depends on the memory access behavior of the program and the way in which the operating system issues block transfer requests.
Keywords: Shared-memory multiprocessor, block transfer support

• Introduction
• Base multiprocessor
  • Simple read requests
• Block transfer support
• Non-block transfer traffic
• Evaluation
• Concluding remarks
• References
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