First consider Figure 17. These graphs
show how the cache size affects the cache access and cycle times in a
direct-mapped and 4-way set-associative cache.
In these graphs (and all graphs in this report),
and 
.
For each cache size, the optimum
array organization parameters were found (these optimum parameters are shown
in the graphs as before; the six numbers associated with each point
correspond to 
, 
, 
,
, 
, and 
in that order), and
the corresponding access and cycle times were plotted. In addition, the
graph breaks down the access time into several components.
Figure 17: Access/cycle time as a function of cache size
There are several observations that can be made from the graphs. Starting
from the bottom, it is clear that the time through the data array decoders
is always longer than the time through the tag array decoders. For all
but one of the
organizations selected, there are more data subarrays
( 
) than tag subarrays ( 
).
This is because the total tag storage is usually much less than
the total data storage.
In all caches shown, the comparator is responsible for a significant portion of the access time. Another interesting trend is that the tag side is always the critical path in the cache access. In the direct-mapped cases, organizations are found which result in very closely matched tag and data sides, while in the set-associative case, the paths are not matched nearly as well. This is due primarily to the delay driving select lines of the output multiplexor.
