Awards for Teaching

On the list of Outstanding Instructors at Illinois in 3 semesters based on student surveys across the entire campus (SP87 for EE382, FA93 for EE382, FA94 for EE309)

Awards for Scholarship

Presidential Young Investigator(PYI) Award, National Science Foundation (Aug 1990-1995)

This award is the most competitive and prestigious award given to junior faculty in the U.S. It is a nationwide competition involving hundreds of faculty members and only 10 were awarded in 1990. The award was given directly from the President’s Office (George Bush in 1990). It provides $62,500 annually plus a matching grant of up to $37,500 for any industrial funding brought in by the award holder, for a total of $100,000 per year for a five year period. I raised more than $37,500 of industrial funding each year.· Inventor Recognition Award for the iSPLICE3 mixed-mode simulation program, Semiconductor Research Corporation, (Oct 1990). This award is made annually to 3 recipients from all SRC-sponsored university researchers in recognition of those who develop their research to a form usable for industry.

Other Awards

Gold Medal from the Association of Professional Engineers of Ontario for outstanding academic achievement at Carleton University (May 1979).

1. Cristian Grecu, Partha Pande, Andre Ivanov, Resve Saleh, “Timing Analysis of Network on Chip
   Architectures for MP-SoC Platforms”, Microelectronics Journal, Elsevier Publications, Volume 36,
   Issue 9, September 2005, pp. 833-845. (NSERC/PMC-Sierra Chair)
2. Zahra Ebadi, S. Mirabbasi, R. Saleh, “The Application of Complex Quantized Feedback to Wireless
   Integrated Receivers”, accepted for publication in August 2005, IEEE Transactions on Circuits and
   Systems. (NSERC/PMC-Sierra Chair, NSERC PGS)
3. Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve Saleh, "Performance
   Evaluation and Design Trade-offs for MP-SoC Interconnect Architectures", IEEE Transactions on
   Computers, Volume 54, Issue 8, August 2005, pp. 1025-1040. (NSERC/PMC-Sierra Chair)
4. Steven J.E. Wilton, Noha Kafafi, James C.H. Wu, Kimberly A. Bozman, Victor O. Aken'Ova,
   Resve Saleh, "Design Considerations for Soft Embedded Programmable Logic Cores", published in
   IEEE Journal of Solid-State Circuits, vol. 40, no. 2, Feb 2005, pp. 485-497. (NSERC/PMC-Sierra
   Chair, NSERC Strategic Grant)
5. Zahra sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, Andre Ivanov, “Design and
   Implementation of Reconfigurable and Flexible Test Access Mechanism (TAM) for System-on-Chip
   (SoC)”, accepted for publication August 2004 in Integration, The VLSI Journal, Special issue on
   "VLSI System-On-Chip", Elsevier Publications. (NSERC/PMC-Sierra Chair)
6. R. Saleh, Z. Hussain, S. Rochel, D. Overhauser, “Clock Verification in the Presence of IR-drop in the
   Power Distribution Network”, IEEE Transactions on CAD of IC and Systems, Vol. 19, No. 6, June
   2000, pp. 635-644. (Simplex Solutions, Inc.)

2006 - 2005

1. Victor Aken’Ova, G. Lemieux, R. Saleh, “An Improved Soft eFPGA Design and Implementation
   Strategy”, IEEE Custom Integrated Circuits Conference, San Jose CA., Sept. 2005. (NSERC/PMCSierra
   Chair, NSERC Strategic Grant)
2. Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh “Effect of traffic
   localization on energy dissipation in NoC-based interconnect infrastructures,” IEEE International
   Symposium on Circuits and Systems, ISCAS 2005, Kobe Japan. (NSERC/PMC-Sierra Chair)
3. D. Sengupta, R. Saleh, “Power-Delay Metrics Revisited for 90nm CMOS Technology”, IEEE
   International Symposium on Quality Electronic Design, March 2005. (NSERC/PMC-Sierra Chair)

2002 - 2004

1. Partha Pratim Pande, Cristian Grecu, Michael Jones, Andre Ivanov, Res Saleh "Evaluation of
   MP-SoC Interconnect Architectures: A Case Study", Proceedings of 4th IEEE International
   Workshop on SoC for Real Time Applications", pp. 253-256, Banff, Canada. (NSERC/PMC-Sierra Chair), IWSOC 2004
2. Cristian Grecu, Partha Pratim Pande, Andre Ivanov, Res Saleh "Structured Interconnect
   Architecture: A Solution for the Non-Scalability of Bus-Based SoCs", Proceedings of GLSVLSI
   2004, pp. 192-195, 26-28th April, Boston. (NSERC/PMC-Sierra Chair)
3. Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh, "A Scalable Communication-
   Centric SoC Interconnect Architecture", IEEE International Symposium on Quality Electronic
   Design, San Jose, California, USA,. (NSERC/PMC-Sierra Chair) March, 2004
4. James C.H. Wu, Victor AkenOva, Steven J.E. Wilton, and Resve Saleh, "SoC Implementation
   Issues for Synthesizable Embedded Programmable Logic Cores", to appear in the Custom Integrated Circuits Conference (CICC). (NSERC/PMC-Sierra Chair), September 2003
5. Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh, "High-Throughput Switch-Based
   Interconnect for Future SoCs", Proceedings of The 3rd IEEE International Workshop on SoC for
   Real Time Applications, pp. 304-310, 2003, Calgary, Canada. (NSERC/PMC-Sierra Chair)
6. Partha Pratim Pande, Cristian Grecu, André Ivanov and Res Saleh, "Switch-Based Interconnect
   Architecture for Future Systems on Chip", Proceedings of SPIE, VLSI Circuits and Systems, Vol.
   5117, pp. 228-237, 2003, Maspalomas, Gran Canaria, Spain. (NSERC/PMC-Sierra Chair)
   Page 4/5
7. Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh, "Design of a Switch for Network
   on Chip Applications", IEEE International Symposium on Circuits and Systems, ISCAS 2003, Vol.
   V, pp. 217-220, Bangkok, Thailand. (NSERC/PMC-Sierra Chair)
8. Stephen Shang, Shahriar Mirabbasi, Resve Saleh, "A Technique for DC-Offset Removal and Carrier Phase Error Compensation in Integrated Wireless Receivers", ISCAS 2003.
9. M. Hamour, R. Saleh, S. Mirabbasi, and A. Ivanov, “Analog IP Design Flow for SoC Applications,”
   ISCAS 2003. (NSERC/PMC-Sierra Chair)
10. M. Nahvi, A. Ivanov and R. Saleh, "Dedicated Autonomous Scan-Based Testing (DAST) for
    Embedded Cores," in proc. IEEE ITC Int. Test Conf., 2002, pp. 1176-1183. (NSERC/PMC-Sierra
    Chair)
11. L. Hong, M. Nahvi, R. Fung, A. Ivanov, R. Saleh, “ Novel Test Methodologies for SoC/IP Designs:
    Implementation and Comparison”, International Workshop on Real-Time System on Chip
    Applications, Banff, AB, July 2002. (NSERC/PMC-Sierra Chair)
12. M. Nahvi, A. Ivanov, R. Saleh, "De-Coupling Test Data Communication and Control/Observation
    for Scan-Based Testing in System-on-Chip", submitted to IEEE International Workshop of Testing
    Embedded Core-based System-Chips 2002. (NSERC/PMC-Sierra Chair)
13. R. Saleh, G. Lim, T. Kadowaki, K. Uchiyama, “SoC Trends for Low-Power Digital Design”,
    International Symposium on Quality in Electronic Design, San Jose, CA., March 2002.
    (Micronet/NSERC/PMC-Sierra Chair)

2001- 1998

1. S. Wilton, R. Saleh “Programmable Logic IP Cores in SoC Design: Opportunities and Challenges”,
   IEEE Custom Integrated Circuits Conference, San Diego, California. (NSERC/PMCSierra
   Chair), May 2001
2. U. Ekambaram, S.M. Kang, R.A. Saleh, “Behavioral-level Envelope-following using Broyden's
   Method”, Proc. of IEEE Int. Conference on Electronics, Circuits and Systems, Pafos, Cyprus, Sept.
   1999, 4p. (NSF PYI Award, at University of Illinois, US)
3. U. Ekambaram, S.M. Kang, R.A. Saleh, “Behavioral Autonomous Steady-State Analysis Using
   Broyden's Method”, Proc. of IEEE Midwest Symposium on Circuits and Systems, Las Cruces, NM, pp. 947-950. (NSF PYI Award, at University of Illinois, US), August 1999
4. S. Hussain, S. Rochel, D. Overhauser, R. Saleh, “Clock Verification in the Presence of IR-Drop in the
   Power Distribution Network”, Proc. of the IEEE Custom Integrated Circuits Conference, San Diego,
   CA., May 1999, pp. 437-440. (Simplex Solutions, Inc.)
5. R. Saleh, D. Overhauser, S. Taylor, "Full-Chip Verification of UDSM Designs", Proc. of IEEE Int. Conference on Computer-Aided Design,SanJose, CA., Nov. 1998, pp. 453-460. (invited)
6. R. Saleh, M. Benoit, P. McCrorie, "Power Distribution Planning", Proc. of IEEE Design, Automation and Test in Europe Conference, Paris,France, Feb. 1998, pp. 265-270.

1997- 1993

1. J. Mueller, B. Antao, and R. Saleh, "A Multifrequency Technique for Frequency Response Computation with Application of Switched-Capacitors Circuits with Nonlinearities," IEEE Trans. on CAD of IC and Syst., vol. 15, no. 7, July 1996, pp. 68-82.
2. R. Saleh, B. Antao, and J. Singh, "Multilevel and Mixed-domain Simulation of Analog Integrated Circuits and Systems," IEEE Trans. on CAD of IC and Syst., Vol. 15, No. 1, January 1996, pp.775-790. (Also included in "Computer-Aided Design of Analog Integrated Circuits", ed. B. Antao, R. Rutenbar, IEEE Publications, 2001.)
3. U. Ekambaram, R. Saleh, "Improved steady-state method applying Broyden’s technique to the shooting method," IEEE Proc. of IEEE Midwest Symposium on Circuits and Systems, Ames, IA, August 1996, pp. 1023-1026.13.
4. Y.-C. Wen, K. Gallivan, and R. Saleh, "Improving Parallel Circuit Simulation using High-Level Waveforms," Proc. of IEEE Int. Symposium on Circuits and Systems, Seattle, WA., pp. 728-731.
   J. Mueller, B. Antao, and R. Saleh, "Rapid Estimation of the Nonlinear Frequency Response of Switched-Capacitor Circuits," Proc. of IEEE Custom Integrated Circuits Conference, Santa Clara, CA., May 1995, pp. 245-248.
5. D. Overhauser and R. Saleh, "Evaluating Mixed-Mode Simulators," Proc. of IEEE Custom Integrated Circuits Conference, Santa Clara, CA., May 1995, pp. 113-120 (invited).
6. B. Antao and R. Saleh, "Simulation Model Transformations for Analog Hardware Description Languages," Proc. of IEEE Custom Integrated Circuits Conference, Santa Clara, CA. May 1995, pp. 537-540.
7. Carlos Pon, R. Saleh, and T. Kwasniewski, "Time Warping-Waveform Relaxation in a distributed Circuit Simulation Environment", Proc. of IEEE Midwest Symposium on Circuits and Systems, Rio de Janeiro, Brazil, 1995, pp. 338-341.
8. Carlos Pon, R. Saleh, and T. Kwasniewski, "Distributed Circuit Simulation using Waveform Relaxation in a Slotted-Ring Architecture," Canadian Conf. on Electrical Engineering and Computer Engineering, Halifax, NS, Sept. 1994, pp. 545-548.
9. R. Saleh, J. Jou, D. Overhauser, X. Xu, and Y. Wang, "Benchmark Circuits for Mixed-Mode Simulation," Proc. of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1994, pp. 441-448. (invited)
10. R. Saleh, D. Rhodes, E. Christen, and B. Antao, "Analog Hardware Description Languages," Proc. of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1994, pp. 349-356. (invited)
11. J. Singh, X. Xu, and R. Saleh, "Simulator Requirements for Usage with Analog HDLs," Int. Conference on Simulation and Hardware Description Languages, Tempe, AZ, Jan. 1994, 4p.
12. G.-G. Hung, Y.-C. Wen, K. Gallivan, and R. Saleh, "Improving the Performance of Parallel Relaxation-based Circuit Simulators," IEEE Trans. on CAD and Syst., Vol. 12, No. 11, Nov. 1993, pp. 1762-1774.
13. J. Singh and R. Saleh, "Frequency Domain Analysis of Switched-Capacitor Circuits Containing Nonidealities," Proc. of IEEE Custom Integrated Circuits Conf., San Diego, CA., May 1993, pp. 18.5.1-18.5.4.

1992- 1988

1. V. Ma, J. Singh, and R. Saleh, "Modeling, Simulation and Optimization of Analog Integrated Circuits," Proc. of IEEE Custom Integrated Circuits Conference, Boston, MA, May 1992, pp. 12.1.1-12.1.4.
2. Y.-C. Ju, R. Saleh, "Incremental Circuit Simulation using Waveform Relaxation," Proc. of ACM/IEEE Design Automation Conference, Anahiem, CA. June 1992, p. 8-11.
3. K. Kubiak, S. Parkes, K. Fuchs, R. Saleh, "Exact Evaluation of Diagnostic Test Resolution", Proc. of the ACM/IEEE Design Automation Conference, Anahiem, CA. June 1992, pp. 347-352.
4. T. Thatcher, R. Saleh, "Automatic Partitioning and Dynamic Mixed-Mode Simulation," Proc. of IEEE Custom Integrated Circuits Conf., May 1992, Boston, MA. , May 1992, pp. 12.7.1-12.7.4.
5. F. Yang and R. Saleh, "Simulation and Analysis of Transient Faults in Digital Circuits," IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, Mar. 1992, pp. 258-264.
6. E. Xia and R. Saleh, "Parallel Waveform-Newton Algorithms for Circuit Simulation," IEEE Trans. on CAD of IC and Syst., Vol. 11, No. 4, Apr. 1992, pp.432-442.
7. J. Singh and R. Saleh, "iMACSIM: A Multilevel Analog Circuit Simulator," Proc. of IEEE Int. Conf. on Comput.-Aided Design, Santa Clara, CA, Nov. 1991, pp. 16-19.
8. Y.-C. Wen, K. Gallivan, and R. Saleh, "Parallel Event-Driven Waveform Relaxation," Proc. of IEEE Int. Conference on Computer Design, Boston, MA, Oct. 1991, pp. 101-104.
9. Y.-C. Ju and R. Saleh, "Identification of Viable Paths using Binary Decision Diagrams," Proc. of IEEE Int. Conference on Computer Design, Boston, MA, Oct. 1991, pp. 638-641.
10. G.-G. Hung, K. Gallivan, and R. Saleh, "Parallel Circuit Simulation based on Nonlinear Relaxation Methods," Proc. of IEEE Int. Symp. on Circuits and Systems, Singapore, May 1991, pp. 2284-2287.
11. Y.-C. Ju and R. Saleh, "Incremental Techniques for the Identification of Statically Sensitizable Critical Paths," Proc. of ACM/IEEE Design Automation Conference, San Francisco, CA, June 1991, pp. 541-546.
12. F. Yang and R. Saleh, "DYNAMO: A Program for the Simulation of Transient Faults in Digital Circuits," Proc. of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1991, pp. 4.3.1-4.3.4.
13. R. Saleh and T. Inoue, "Current Problems, Current Solutions and Future Trends in Circuit Simulation," Invited Paper, Proc. of the IECE of Japan, Vol. J74-A, No. 8, Aug. 1991, pp. 1188-1196. (Japanese). Also published as, "Enhanced Circuit Simulation. Expectations, problems, implementation and integration.", Electronic Communications in Japan, v. 74, n. 11, Nov. 1991., p. 101-111. (English)
14. Y.-C. Ju, V. B. Rao, and R. Saleh, "Verification and Optimization of Macromodels," IEEE Trans. on CAD of IC and Syst., Vol. 10, No. 8, Aug. 1991,pp. 957-967. (Also included in "Computer-Aided Design of Analog Integrated Circuits", ed. B. Antao, R. Rutenbar, IEEE Publications, 2001.)
15. R. Saleh and J. White, "Accelerating Relaxation Algorithms for Circuit Simulation using Waveform Newton, Stepsize Refinement," IEEE Trans.on CAD of IC and Syst., Vol. 9, No. 9, Sept. 1990, pp. 951-958.
16. E. Acuna, J. Dervenis, A. Pagones, F. Yang, and R. Saleh, "Simulation Techniques for Mixed Analog and Digital Circuits," IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, Apr. 1990, pp. 353-363.
17. Y.-C. Ju, F. Yang, and R. Saleh, "Mixed-mode Incremental Simulation and Concurrent Fault Simulation," Proc. of IEEE Int. Conference on Computer-Aided Design, Santa Clara, CA, Nov. 1990, pp. 158-161.
18. G.-G. Hung, Y.-C. Wen, K. Gallivan, and R. Saleh, "Parallel Circuit Simulation using Hierarchical Relaxation," IEEE/ACM Design Automation Conference, Orlando, FL, June 1990, pp. 394-399.
19. G. Choi, R. Iyer, and R. Saleh, "A Fault Behavior Model for an Avionic Microprocessor: A Case Study," Int. Working Conf. on Dependable Computing for Critical Applications, Santa Barbara, CA, Aug. 1989, pp. 71-77.
20. R. Saleh, R. Rudell, and S. Parkes, "Experiments with Global Flow Analysis," Int. Logic Synthesis Workshop., May 1989, 4p.
21. R. Saleh, E. Acuna, J. Dervenis, and A. Pagones, "iSPLICE3: A New Simulation Program for Mixed Analog/Digital VLSI Circuits," Proc. of IEEE Custom Integrated Circuits Conference, May 1989, San Diego, CA, pp. 13.1.1-13.1.4.
22. R. Saleh, K. Gallivan, I. Hajj, M. Chang, D. Smart, and T. Trick, "Circuit Simulation on Supercomputers," Proc. of IEEE, Vol. 77, No. 12, Dec. 1989, pp. 915-931.
23. R. Saleh and A. R. Newton, "The Exploitation of Latency and Multirate Behavior using Nonlinear Relaxation for Circuit Simulation," IEEE Trans. on CAD of IC and Syst., Vol. 8, No. 12, Dec. 1989, pp. 1286-1298.
24. R. Roy, T. Niermann, J. Patel, J. Abraham, and R. Saleh, "Compaction of ATPG-Generated Test Set for Sequential Circuits," Proc. of IEEE Int. Conference on Computer-Aided Design, Santa Clara, CA, Nov. 1988, pp. 382-385.
25. R. Saleh, K. Gallivan, P. Koss, and S. Lo, "A Comparison of Parallel Relaxation-based Circuit Simulation Techniques," Electro '88, Boston, MA, May 1988.
    

1987 - 1982

1. R. Saleh, D. Webber, E. Xia, and A. S. Vincentelli, "Parallel Waveform-Newton Algorithms for Circuit Simulation," Proc. of IEEE Int. Conference On Computer Design, Rye Brook, NY, Oct. 1987, pp. 660-663.
2. R. Saleh and A. R. Newton, "Event-driven Relaxation-based Multirate Integration Scheme for Circuit Simulation," Proc. of IEEE Int. Symposium on Circuits and Systems, Philadelphia, PA, May 1987, pp. 600-603.
3. J. White, R. Saleh, A. S. Vincentelli, and A. R. Newton, "Accelerating Relaxation Algorithms using Waveform Newton, Stepsize Refinement and Parallel Techniques," Proc. of IEEE Int. Conference on Computer-Aided Design, Santa Clara, CA, Nov. 1985, pp. 5-7.
4. Y. H. Kim, J. Kleckner, R. Saleh, and A. R. Newton, "Electrical-Logic Simulation", Proc. of IEEE Int. Conference on Computer-Aided Design, Santa Clara, CA, Nov. 1984, pp. 7-9.
5. R. Saleh, J. Kleckner, and A. R. Newton, "Iterated Timing Analysis in SPLICE1," Proc. of IEEE Int. Conference on Computer-Aided Design, Santa Clara, CA, Sept. 1983, pp. 139-140.
6. J. Kleckner, R. Saleh, and A. R. Newton, "Electrical Consistency in Schematic Simulation," Proc. of IEEE Int. Conference on Circuits and Computers, New York, NY, Oct.1982, pp. 30-34.
7. M. Caughey, D. Klett, J. Peacock, K. Dwivedi, T. Lalonde, and R. Saleh, "A Rapid Implementation of CAD for IC Design," Proc. of IEEe Custom Integrated Circuits Conference, Rochester, NY, Oct. 1982. 2p.