SoC Group Publications by Topic
Analog/Mixed Signal Design
FPGA's
SOC Design
SOC Test
SOC Verification

Andre Ivanov - publications
Alan Hu - publications
Guy Lemieux - publications
Mark Greenstreet - publications

Resve Saleh - publications
Shahriar Mirabbasi - publications
Steve Wilton - publications

• B. Rahmatian and S. Mirabbasi, “A Low-Power 75-dB Digitally Programmable Variable-Gain Amplifier in 0.18µm CMOS,” to appear in Canadian Journal of Electrical and Computer Engineering.
• S. Sheikhaei, S. Mirabbasi, A. Ivanov, “A 43mW Single-Channel 4GS/s 4-Bit Flash ADC in 0.18µm CMOS,” to be presented at IEEE Custom Integrated Circuits Conference (CICC), September 2007.
• S. Jalali Mazlouman, S. Sheikhaei, and S. Mirabbasi, “A Prototype Implementation of a Two-Channel Frequency-Translating Hybrid ADC,” presented at the 50th IEEE International Midwest Symposium on Circuits and Systems (NEWCAS/MWSCAS), Montreal, Canada, August 2007.
• S. Jalali Mazlouman and S. Mirabbasi, “A Frequency-Translating Hybrid Architecture for Wideband Analog-to-Digital Converters,”  IEEE Transactions on Circuits and Systems II, vol. 54, no. 7, July 2007, pp. 576-580.
• B. Rahmatian and S. Mirabbasi, “A low-Power 75-dB Digitally Programmable CMOS Variable-Gain Amplifier,” Presented at the IEEE Canadian Conf. on Electrical and Computer Engineering (CCECE), April 2007. (Best Student Paper Award)
• D. Ho and S. Mirabbasi, “Low-Power Design Considerations for CMOS Low-Noise Amplifiers,” Presented at the 20th IEEE Canadian Conf. on Electrical and Computer Engineering (CCECE), Apr. 2007.
• S. Jalali Mazlouman, A. Mahanfar, and S. Mirabbasi, “A Low-Power CMOS Modulator for Ultra-Wideband (UWB) Transmitters,” Presented at the 20th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), April 2007.
• K. Allidina and S. Mirabbasi, “A Widely Tunable Active RF Filter Topology,” Presented at the IEEE International Symposium on Circuits and Systems, ISCAS 2006.
• M. Hekmat, S. Mirabbasi, and M. Hashemi, “On the Behaviour of Passive Guard-Rings in Lightly-Doped Substrates,” Presented at the IEEE International Symposium on Circuits and Systems, ISCAS 2006.
• R. Molavi, S. Mirabbasi, and R. Saleh, “A High-Speed Low-Energy Dynamic PLA Using Input-Isolation Scheme,” Presented at the IEEE International Symposium on Circuits and Systems, ISCAS 2006.
• S. Au, S. Mirabbasi, L. Lampe, and R. Schober, “Per-Survivor Processing Viterbi Decoder for Bluetooth Applications,” Presented at the IEEE International Symposium on Circuits and Systems, ISCAS 2006.
• Z.S. Ebadi, S. Mirabbasi, and R. Saleh, “The Application of Complex Quantized Feedback in Integrated Wireless Receivers,” to appear in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 3, March 2006, pp. 594-603.
• P. Sameni, C. Siu, S. Mirabbasi, H. Djahanshahi, M. Hamour, K. Iniewski, and J. Chana, “Modeling and Characterization of VCOs with MOS Varactors for RF Transceivers,” EURASIP Journal on Wireless Communications and Networking, Special issue on CMOS RF Circuits for Wireless Applications, vol. 2006, Article ID 93712, 12 pages, 2006.
• R. Rosales, and M.K. Jackson, “Silicon Bipolar Circuits for Wideband FM CATV Transmission,” Proceedings ESSCIRC 2005, Grenoble, France, pp.307-310.
• S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 0.18µm CMOS Pipelined Encoder for a 5GS/s 4-Bit Flash Analogue-to-Digital Converter,” IEEE Canadian Journal of Electrical and Computer Engineering, Vol. 30, Issue 4, Fall 2005, pp. 183–187.
• D. Ho and S. Mirabbasi, “A Low-Voltage Low-Power Low-Noise Amplifier for Wireless Sensor Networks,” IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2006.
• M. Hekmat, S. Mirabbasi, and M. Hashemi, “Ground Bounce Calculation due to Simultaneous Switching in Deep Sub-micron Integrated Circuits, ”IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe, Japan, pp. 5617-5620.
• N. Nouri and S. Mirabbasi, “A 900MHz-2GHz Low-Swing Low-Power 0.18µm CMOS PLL” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2005, pp. 1566-1569.
• P. Sameni, C. Siu, K. Iniewski, M. Hamour, S. Mirabbasi, H. Djahanshahi, and J. Chana, ”Modeling of MOS Varactors and Characterizing the Tuning Curve of a 5-6 GHz LC VC), ” IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe, Japan, pp.
• P. Sameni, C. Siu, K. Iniewski, S. Mirabbasi, H. Djahanshahi, M. Hamour, and J. Chana, “Characterization and Modeling of Accumulation-Mode MOS Varactors,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2005, pp. 1562-1565.
• R. Molavi, S. Mirabbasi, and M. Hashemi, “A Wideband CMOS LNA Design Approach, ” IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe, Japan, pp. 5107-5010.
• R. Molavi, S. Mirabbasi, and M. Hashemi, “SNR-Based Design Technique for Broadband LNAs,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2005, pp. 835-838.
• S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 0.35um CMOS Comparator Circuit For High-Speed ADC Applications” IEEE International Symposium on circuits and Systems, ISCAS 2005, Kobe, Japan, pp. 6134-6137.
• S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “A 4-Bit 5GS/s Flash A/D Converter in 0.18um CMOS, ”IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe, Japan, pp. 6138-6141.
• S. Sheikhaei, S. Mirabbasi, and A. Ivanov, “An Encoder for a 5GS/s 4-Bit Flash ADC in 0.18µm CMOS,” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2005, pp. 698-701. (Best Student Paper Award)
• Siu, K. Iniewski, M. Hamour, S. Mirabbasi, H. Djahanshahi, and J. Chana, “Modeling of MOS Varactors and Characterizing the Tuning Curve of a 5-6 GHz LC VCO,” IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe, Japan, pp. 5071-5074.
• P. Sameni and S. Mirabbasi, “A 1/8-Rate Clock and Data Recovery Architecture For High-Speed Communication Systems,” IEEE International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, Canada, vol. 4, pp. 305-308.
• P. Sameni and S. Mirabbasi, “A Fully Differential High-Speed Low Voltage Double-Edge Triggered Flip-Flop (DETFF),” Proceedings of IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), May 2004, pp. 1459-1462.
• S. Mirabbasi and K. Martin, “Design of prototype filter for near-perfect-reconstruction overlapped complex-modulated transmultiplexers,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 50, No. 8, August 2003, pp. 456-469.
• S. Shang, S. Mirabbasi and R. Saleh, “A Technique for DC-Offset Removal and Carrier Phase Compensation in Integrated Wireless Receivers,” IEEE International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, vol. 1, pp. 173-176.

• B.R. Quinton, M.R. Greenstreet, S.J.E. Wilton, “Practical Asynchronous Interconnect Network Design,” to appear in IEEE Transactions on Very-Large Scale Integration (VLSI).
• J. Lamoureux, G.G. Lemieux, S.J.E. Wilton, “GlitchLess: Dynamic Power Minimization in FPGAs through Edge Alignmnet and Glitch Filtering,” to appear in IEEE Transactions on VLSI.
• C.W. Yu, J. Lamoureux, S. Wilton, P.H.W. Leong, W. Luk, “The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units,” to appear in Southern Programmable Logic Conference, Bariloche, Argentina, March 2008.
• J. Yu, G. Lemieux, C. Eagleston, “Vector Processing as a Soft-core CPU Accelerator,” to appear at ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, 10 pp., February 2008.
• J. Yu, G. Lemieux, “A Case for Soft Vector Processors in FPGAs,” refereed poster to appear at IEEE International Conference on Field-Programmable Technology, Kitakyushu, Japan, 4 pp., December 2007.
• S. Chin, S.J.E. Wilton, “Memory Footprint Reduction For FPGA Routing Algorithms,” in the IEEE International Conference on Field-Programmable Technology, Kokurakita, Japan, December 2007, pp. 1-8. (Best Paper Award )
• E. Lee, G. Lemieux, S. Mirabbasi, “Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays,” Journal of VLSI Signal Processing, Springer Netherlands, Transactions on VLSI, October 4, 2007.
• B. Quinton, S.J.E. Wilton, “Embedded Programmable Logic Core Enhancements for System Bus Interfaces,” in the International Conference on Field-Programmable Logic and Applications, Amsterdam, August 2007, pp. 202-209.
• C.H.Ho, C.W.Yu, P.H.W. Leong, W. Luk, S.J.E. Wilton, “Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications,” in the International Conference on Field-Programmable Logic and Applications, Amsterdam, August 2007, pp. 196-201. Distinguished Paper Award
• J. Lamoureux, S.J.E. Wilton, “Clock-Aware Placement for FPGAs,” in the International Conference on Field-Programmable Logic and Applications, Amsterdam, August 2007, pp. 124-131.
• B.R. Quinton, S.J.E. Wilton, “Programmable Logic Core Based Post-Silicon Debug For SoCs,” in the 4th IEEE Silicon Debug and Diagnosis Workshop, Germany, May 2007.
• D. Yeager, D. Chiu, G. Lemieux, “Congestion Estimation and Localization in FPGAs: A Visual Tool for Interconnect Prediction,” International Workshop on System-Level Interconnect Prediction, Austin, TX, March 2007.
• J. Lamoureux, G.G. Lemieux, S.J.E. Wilton, “GlitchLess: An Active Glitch Minimization Technique for FPGAs,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2007.
• S.J.E. Wilton, C.H. Ho, P.H.W. Leong, W. Luk, B. Quinton, “A Synthesizable Datapath-Oriented Embedded FPGA Fabric,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 2007.
• D. Grant, G. Lemieux, “Perturber: Semi-Synthetic Circuit Generation Using Ancestor Control for Testing Incremental Place and Route,” IEEE International Conference on Field-Programmable Technology, Bangkok, pp. 189-195, December 2006.
• E. Lee, G. Lemieux, S. Mirabbasi, “Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays,” IEEE International Conference on Field-Programmable Technology, Bangkok, pp. 89-96, December 2006.
• N. Chan King Choy, S.J.E. Wilton, “Activity-Based Power Estimation and Characterization of DSP and Multiplier Blocks in FPGAs,” International Conference on Field-Programmable Technology (poster presentation), Bangkok, Thailand, December 2006.
• M. Tom, D. Leong, G. Lemieux, “Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs,” IEEE International Conference Computer-Aided Design, San Jose, November 2006.
• D. Grant, S. Chin, G. Lemieux, “Semi-synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Place and Route Tools,” refereed poster at ACM/SIGDA International Symposium on Field-Programmable Logic, Madrid, August 2006.
• J. Lamoureux, S.J.E. Wilton, “Activity Estimation for Field-Programmable Gate Arrays,” International Conference on Field-Programmable Logic and Applications, Madrid, Spain, August 2006.
• S.Y.L. Chin, C.S.P. Lee, S.J.E. Wilton, “Power Implications of Implementing Logic using FPGA Embedded Memory Arrays,” International Conference on Field-Programmable Logic and Applications, Madrid, Spain, August 2006.
• C.H. Ho, P.H.W. Leong, W. Luk, S.J.E. Wilton, S. Lopez-Buedo, “Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs,” in the IEEE International Symposium on Field-Programmable Custom Computing Machines, Napa, CA, Apr. 2006.
• Lamoureux, S.J.E. Wilton, “FPGA Clock Network Architecture: Flexibility vs. Area and Power,” in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, California, Feb 2006.
• A. Yu, G. Lemieux, “Defect Tolerance: Impact of Granularity,” IEEE International Conference on Field-Programmable Technology, Singapore, pp. 189-196, December 2005.
• B.R. Quinton, S.J.E. Wilton, “Post-Silicon Debug Using Programmable Logic Cores,” in the International Conference on Field-Programmable Technology, Singapore, December 2005.
• C.T. Chow, L.S.M. Tsui, P.H.W. Leong, W. Luk, S. Wilton, “Dynamic Voltage Scaling for Commerical FPGAs,” in the International Conference on Field-Programmable Technology, Singapore, December 2005. (Best Paper Award)
• P. Hallschmid, S.J.E. Wilton, “Routing Architecture Optimizations for High-Density Embedded Programmable IP Cores,” to appear in IEEE Transactions on Very-Large Scale Integration Systems, Vol. 13, No. 11, November 2005, pp. 1320-1324.
• B.R. Quinton, M. Greenstreet, S.J.E. Wilton, “Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow,” in the IEEE International Conference on Computer Design, October 2005, pp. 267-274.
• V. Aken'ova, G. Lemieux, Resve Saleh, “An Improved Soft eFPGA Design and Implementation Strategy,” Custom Integrated Circuits Conference, San Jose, California, pp. 179-182, September 2005.
• A. Yu, G. Lemieux, “Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement,” Int'l Conference on Field-Programmable Logic and Applications, Tampere, Finland, pp. 255-262, August 2005.
• J. Lamoureux and S.J.E. Wilton, “On the Interaction Between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays,” Journal of Low Power Electronics, Vol. 1, No. 2, August 2005, pp. 119-132.
• M. Tom, G. Lemieux, “Logic Block Clustering of Large Designs for Channel-Width Constrained FPGAs” to appear in Design Automation Conference (DAC 2005), Anaheim, California, June 2005
• S.W. Oldridge and S.J.E. Wilton, “A Novel FPGA Architecture Supporting Wide, Shallow Memories,” in IEEE Transactions on Very-Large Scale Integration (VLSI) Systems, Vol. 13, Issue 6, June 2005, pp. 758-762.
• B.R. Quinton, S.J.E. Wilton, “Concentrator Access Networks for Programmable Logic Cores on SoCs” in the IEEE International Symposium on Circuits and Systems, May 2005, pp. 45-48.
• K.K.W. Poon, S.J.E. Wilton, A. Yan, “A Detailed Power Model for Field-Programmable Gate Arrays,” in ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, Issue 2, April 2005, pp. 279-302. .
• Z. Kwok and S.J.E. Wilton, “Register File Architecture Optimization in a Coarse-Grained Reconfigurable Architecture,” to appear in IEEE Symposium on Field-Programmable Custom Computing Machines, April 2005.
• T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, “Reconfigurable Computing: Architectures and Design Methods,” IEE Proceedings: Computer & Digital Techniques, Vol. 152, No. 2, March 2005, pp. 193-208. . Included in B.M. Al-Hashimi (Ed.), “System on Chip: Next Generation Electronics,” IET, ISBN 0-86341-552-0/4, 2006.
• S.J.E. Wilton, N. Kafafi, J. Wu, K. Bozman, V. Aken'Ova, R. Saleh, “Design Considerations for Soft Embedded Programmable Logic Cores,” IEEE Journal of Solid-State Circuits, vol. 40, no. 2, Feb 2005, pp. 485-497.
• G. Lemieux, E. Lee, M. Tom, A. Yu, “Directional and Single-Driver Wiring in FPGA Interconnect” IEEE International Conference on Field-Programmable Technology (FPT), December 2004. (Best Paper Award)
• S.J.E. Wilton, N. Kafafi, B. Mei, S. Vernalde, “Interconnect Architectures for Modulo-Scheduled Coarse-Grained Reconfigurable Arrays,” in the International Conference on Field-Programmable Technology, Brisbane, Australia, December 2004, pp. 33-40.
• T. Wong, S.J.E. Wilton, “Placement and Routing for Non-Rectangular Embedded Programmable Logic Cores in SoC Design,” in the International Conference on Field-Programmable Technology, Brisbane, Australia, December 2004, pp. 65-72.
• A. Yan, S.J.E. Wilton, “Sequential Synthesizable Embedded Programmable Logic Cores for System-on-Chip,” in the IEEE Custom Integrated Circuits Conference , Orlando, FL, October 2004.
• S.J.E. Wilton, S-S. Ang, W. Luk, “The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays,” in International Conference on Field-Programmable Logic and its Applications, Antwerp, Belgium, August 2004. Included in Lecture Notes in Computer Science 3203, Springer-Verlag, pp. 719-728. (Best Paper Award)
• S.J.E. Wilton, C.W. Jones, J. Lamoureux, ”An Embedded Flexible Content-Addressable Memory Core for Inclusion in a Field-Programmable Gate Array,” in the IEEE International Symposium on Circuits and Systems, Vancouver, B.C., May 2004, Vol. II, pp. 885-888. (refereed poster)
• A. Yan, S.J.E. Wilton, “Product Term Embedded Synthesizable Logic Cores,” in the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, Dec. 2003, pp. 162-169. (Best Paper Award)
• S.W. Oldridge, S.J.E. Wilton, “Placement and Routing for FPGA Architectures Containing Wide Shallow Memories,” in the IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, December 2003, pp. 154-161.
• J. Lamoureux and S.J.E. Wilton, “On the Interaction between Power-Aware FPGA CAD Algorithms,” in International Conference on Computer-Aided Design (ICCAD), November 2003.
• J.C.H. Wu, V. Aken'Ova, S.J.E. Wilton, R. Saleh, “SoC Implementation Issues for Synthesizable Embedded Programmable Logic Cores,” in the IEEE Custom Integrated Circuits Conference, San Jose, CA, Sept. 2003, pp. 45-48.
• S.J.E. Wilton, “Implementing Logic in FPGA Memory Arrays: Heterogeneous Memory Architectures,” in the IEEE International Conference on Field-Programmable Technology, December 2002, pp. 142-149.
• K. Poon, A. Yan, S.J.E. Wilton, “A Flexible Power Model for FPGAs,”in the 12th International Conference on Field-Programmable Logic and Applications, Sept 2002. Included in Lecture Notes in Computer Science 2438, Springer-Verlag, pp. 48-58.
• E. Lin, S.J.E. Wilton, “The Architecture of Dual-Mode FPGA Embedded System Blocks,” in IEEE Custom Integrated Circuits Conference, May 2002.
• A. Yan, R. Cheng, S.J.E. Wilton, “On the Sensitivity of FPGA Architectural Conclusions to the Experimental Assumptions, Tools, and Techniques,” in the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, Feb. 2002, pp. 147-156.
• E. Lin, S.J.E. Wilton, “Macrocell Architectures for Product Term Embedded Memory Arrays,” in 11th International Conference on Field-Programmable Logic and Applications, Aug 2001. (Best Paper Award).
• S.J.E. Wilton, R. Saleh, “Progammable Logic IP Cores in SoC Design: Opportunities and Challenges,”in the IEEE Custom Integrated Circuits Conference, May 2001.
• S.W. Oldridge, S.J.E. Wilton, “A Novel FPGA Architecture Supporting Wide Shallow Memories,” in the IEEE Custom Integrated Circuits Conference, San Diego, CA, May 2001, pp. 75-78.
• S.J.E. Wilton, “A Crosstalk-Aware Timing-Driven Router for FPGAs,”in the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Feb. 2001.
• W.W. Cheng, S.J.E. Wilton, B. Hamidzadeh, “FPGA Implementation of a Prototype WDM On-Line Scheduler,” in the 10th International Conference on Field Programmable Logic and Applications, August 2000. (refereed poster)
• S.J.E. Wilton, J. Rose, Z.G. Vranesic, “Structural Analysis and Generation of Digital Circuits with Memory,” IEEE Transactions on Very-Large Scale Integration Systems , vol. 9, no. 1, February 2001, pp.223-226.
• S.J.E. Wilton, “Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19, No. 1, Jan. 2000, pp. 56-68.

• Cristian Grecu, Andre Ivanov, Resve Saleh, Partha Pande, “Testing Network-on-Chip Communication Fabrics,” IEEE Transactions on Computer-Aided Design, December 2007, pp. 2201-2214.
• Zahra sadat Ebadi, Resve Saleh, “ Adaptive Compensation of RF Front-end Nonidealities in Direct Conversion Receivers,” accepted to IEEE Transactions on Circuits and Systems II, December 2007.
• Xiongfei Meng, Resve Saleh, Karim Arabi, “ Layout of Decoupling Capacitors in IP Blocks for 90nm CMOS,” accepted to IEEE Transactions on Very-Large Scale Integration Systems, November 2007.
• Victor Aken'Ova, Guy Lemieux, Resve Saleh, “Soft++: An Improved Embedded FPGA Methodology for SoC Designs,” accepted to IEEE Transactions on Very-Large Scale Integration Systems, September 2007.
• P. Teehan, M. Greenstreet, G. Lemieux, “A Survey and Taxonomy of GALS Design Styles,” IEEE Design & Test of Computers, 24(5), Sept.-Oct., 2007, pp. 418-428.
• D. Sengupta, R. Saleh, “Constraint-based Voltage Island Partitioning,” accepted to IEEE Midwest Symposium on Circuits and Systems, August 2007.
• Peter Hallschmid, Resve Saleh, “Fast Design Space Exploration using Local Regression Modeling with Applications to ASIPs,” accepted to IEEE Transactions on Computer-Aided Design, August 2007.
• C. Grecu, L. Anghel, P. Pande, A. Ivanov, R. Saleh “ Essential Fault-Tolerance Metrics for NoC Infrastructures,” accepted to IEEE International On-line Testing Symposium, IOLTS 2007.
• P. Hallschmid, R. Saleh, “Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling,” IEEE/ACM Design Automation Conference, June 2007.
• A. Kedia, R. Saleh, “Power Reduction of On-Chip Serial Links,” IEEE International Symposium on Circuits and Systems, May 2007.
• Karim Arabi, Resve Saleh, Xiongfei Meng, “Power Supply Noise in SoCs: Metrics, Management and Measurement,” IEEE Design and Test of Computers, May-June 2007, pp. 236-244.
• X. Meng, K. Arabi, R. Saleh, “A Novel Active Decap Circuit in 90nm CMOS,” IEEE International Symposium on Circuits and Systems, May 2007.
• U. Al-Saiari, R. Saleh, “Power, Delay and Yield Analysis of BIST/BISR PLA using Column Redundancy,” IEEE International Symposium on Quality Electronic Design, March 2007, pp. 703-708.
• M. Alimadadi, S. Sheikhaei, G. Lemieux, S. Mirabbasi, P. Palmer, “A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter,” IEEE International Solid State Circuits Conference (ISSCC), San Francisco, February 2007, pp. 532-533.
• Dipanjan Sengupta, Resve Saleh, “Supply and Threshold Selection using Generalized Power-Delay Metrics for DSM CMOS,” IEEE Transactions on Computer-Aided Design, Vol. 26, Issue 1, Jan. 2007, pp. 183-189.
• Cristian Grecu, André Ivanov, Resve Saleh, Partha Pratim Pande, “NoC Interconnect Yield Improvement Using Crosspoint Redundancy,” IEEE Defect and Fault Tolerance in VLSI Systems Symposium, Oct. 2006, Washington, DC.
• Santosh Sood, Mark Greenstreet, Resve Saleh, “A Novel Distributed and Interleaved FIFO for Source-Synchronous Interconnect ,” IEEE VLSI Design and Test Symposium, Goa, India. August 2006.
• Sohaib Majzoub, Resve Saleh, H. Diab, “Reconfigurable Platform Evaluation Through Application Mapping and Performance Analysis,” Int. Symp. on Signal Processing and Information Technology, August 2006, Vancouver, Canada.
• Cristian Grecu, André Ivanov, Resve Saleh, E. Sogomonyan, Partha Pratim Pande, “On-line Fault Detection and Location for NoC Interconnect,” IEEE International On-line Testing Symposium, IOLTS 2006, pp.145-150, July 2006, Como, Italy.
• R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P. Pande, C. Grecu, A. Ivanov, “System-on-Chip: Reuse and Integration,” Proceedings of the IEEE, Vol. 94, No. 6, June 2006, pp. 1050-1069.
• U. Al-Saiari, R. Saleh, “Testable and Self-repairable Structured Logic Design ,” IEEE International Symposium on Circuits and Systems, May 2006.
• C. Grecu, P. Pande, A. Ivanov, R. Saleh “ BIST for NoC Interconnect Infrastructures,” IEEE VLSI Test Symposium 2006.
• P. Hallschmid, R. Saleh, “Fast Configuration of an Energy-Efficient Branch Predictor,” IEEE International Symposium on VLSI, March 2006.
• Victor Aken’Ova, R. Saleh, “A Soft++ eFPGA Physical Design Approach with Case Studies in 180nm and 90nm Strategy,” IEEE Symposium on VLSI, March 2006.
• X. Meng, K. Arabi, R. Saleh, “Novel Decoupling Capacitor Designs for sub-90nm CMOS Technology,” IEEE International Symposium on Quality in Electronic Design, March 2006.
• Partha Pande, Cristian Grecu, Andre Ivanov, Resve Saleh, Giovanni DeMicheli, “Design, Test and CAD for Network on Chip: Challenges and Solutions,” IEEE Design and Test of Computers, Volume 22, Issue 5, September/October 2005, pp. 404-413.
• V. Aken'ova, G. Lemieux, Resve Saleh, “An Improved Soft eFPGA Design and Implementation Strategy,” Custom Integrated Circuits Conference, San Jose, California, pp. 179-182, September 2005.
• Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve Saleh, “Performance Evaluation and Design Trade-offs for MP-SoC Interconnect Architectures,” IEEE Transactions on Computers, Volume 54, Issue 8, August 2005, pp. 1025-1040.
• A. Yan, S.J.E. Wilton, “Product-Term Based Synthesizable Embedded Programmable Logic Cores,” IEEE Transactions on VLSI, Vol. 14, No. 5, May 2006, pp. 474-488.
• Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Res Saleh “Effect of traffic localization on energy dissipation in NoC-based interconnect infrastructures” To appear in IEEE International Symposium on Circuits and Systems, ISCAS 2005, Kobe Japan
• D. Sengupta, R. Saleh, “Power-Delay Metrics Revisited for 90nm CMOS Technology,” IEEE International Symposium on Quality Electronic Design, March 2005. (NSERC/PMC-Sierra Chair)
• Partha Pratim Pande, Cristian Grecu, Michael Jones, Andre Ivanov, Res Saleh, “Evaluation of MP-SoC Interconnect Architectures, Proceedings of 4th IWSOC, 19th-21st July 2004, Banff, Alberta, Canada.
• Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh “Structured Interconnect Architecture: A Solution for the Non-Scalability of Bus-Based SoCs” Accepted in GLSVLSI 2004, pp. 192-195, 26-28th April, Boston.
• Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh, “A Scalable Communication-Centric SoC Interconnect Architecture,” in IEEE International Symposium on Quality Electronic Design, ISQED 2004 held in San Jose, California, USA, 22-24 March, 2004.
• James C.H. Wu, Victor AkenOva, Steven J.E. Wilton, and Resve Saleh, “SoC Implementation Issues for Synthesizable Embedded Programmable Logic Cores,” to appear in the Custom Integrated Circuits Conference (CICC), September 2003.
• Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh, “High-Throughput Switch-Based Interconnect for Future SoCs, ”Proceedings of The 3rd IEEE International Workshop on SoC for Real Time Applications, pp. 304-310, 2003, Calgary, Canada
• M. Hamour, R. Saleh, S. Mirabbasi, and A. Ivanov, “Analog IP Design Flow for SoC Applications,” IEEE International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, vol. 4, pp. 676-679.
• Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh, “Design of a Switch for Network on Chip Applications,” IEEE International Symposium on Circuits and Systems, ISCAS 2003, Vol. V, pp. 217-220, Bangkok, Thailand.
• Stephen Shang, Shahriar Mirabbasi, Resve Saleh, “A Technique for DC-Offset Removal and Carrier Phase Error Compensation in Integrated Wireless Receivers,” ISCAS 2003.
• Partha Pratim Pande, Cristian Grecu*, André Ivanov and Res Saleh, “Switch-Based Interconnect Architecture for Future Systems on Chip,” Proceedings of SPIE, VLSI Circuits and Systems, Vol. 5117, pp. 228-237, 2003, Maspalomas, Gran Canaria, Spain
• N. Kafafi, K. Bozman, S.J.E. Wilton, “Architectures and Algorithms for Synthesizable Embedded Programmable Logic Cores,” in the ACM International Symposium on Field-Programmable Gate Arrays, Monterey, CA, Feb 2003, pp. 1-9.
• M. Nahvi, A. Ivanov, R. Saleh, “De-Coupling Test Data Communication and Control/Observation for Scan-Based Testing in System-on-Chip,” submitted to IEEE International Workshop of Testing Embedded Core-based System-Chips 2002.
• R. Saleh, G. Lim, T. Kadowaki, K. Uchiyama, “SoC Trends for Low-Power Digital Design,” International Symposium on Quality in Electronic Design, San Jose, CA., March 2002. (Micronet/NSERC/PMC-Sierra Chair)
• S. Wilton, R. Saleh “Programmable Logic IP Cores in SoC Design: Opportunities and Challenges,” IEEE Custom Integrated Circuits Conference, San Diego, California. , May 2001.

• Cristian Grecu, Andre Ivanov, Resve Saleh, Partha Pande, “Testing Network-on-Chip Communication Fabrics,” IEEE Transactions on Computer-Aided Design, Vol, 26, December 2007, pp. 2201-2214.
• Mollah A. K. M. K., Rosales R., Tabatabaei S., Cicalo J., Ivanov A. , “Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients,” IEEE Transactions on Circuits and Systems I: Vol. 54, Issue 12, Dec. 2007 pp.2669-2682
• Z. Fantai, A. Ivanov, “MPM-Based Interconnect Architecture for the Design of 3D MP-SOCs,” Chinese Journal of Electron Devices, Vol. 30, No. 4, August 2007, pp. 1—4.
• Q. Xu, B. Wang, A. Ivanov, E. Young, “Test Scheduling for BISTed Embedded SRAMs with Data Retention Faults,” IET Computers and Digital Techniques (Formally IEE Proceedings), Vol. 1, No. 3, May 2007, pp. 256-264.
• H.G. Schulze, R. B. Foist, A. I. Jirasek, A. Ivanov, R.F.B. Turner, “Two-Point Maximum Entropy Noise Discrimination in Spectra Over a Range of Baseline Offsets and Signal-to-Noise Ratios,” Applied Spectroscopy, Vol. 61, No. 2., Feb. 2007, pp. 157 – 164.
• Zahra sadat Ebadi, Alireza Nasiri Avanaki, Resve Saleh, Andre Ivanov, “Design and Implementation of Reconfigurable and Flexible Test Access Mechanism (TAM) for System-on-Chip (SoC),” Integration, The VLSI Journal, Special issue on VLSI System-On-Chip, Elsevier Publications, Vol. 40, Issue 2, Feb. 2007, pp. 149-160.
• Josh Yang, Baosheng Wang, Yuejian Wu and Andre Ivanov, “Fast Detection of Data Retention Faults and Other SRAM Cell Open Defects,” in the IEEE Transactions on Computer Aided Design (TCAD) of Integrated Circuits and Systems, Vol. 25, Jan 2006, pp 167-180.
• Baosheng Wang, Andy Kuo, Touraj Farahmand, Andr Ivanov, Yong B. Cho and Sassan Tabatabaei, “A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices,” Journal of Electronic Testing: Theory and Application (JETTA), Vol. 21, No. 6, pp. 621-630, December 2005
• A. Kuo, T. Farahmand, S. Tabatabaei, A. Ivanov, “Crosstalk Bounded Uncorrelated Jitter (BUJ) for High-speed Interconnects,” IEEE Trans. on Instrumentation and Measurement, Vol. 54, No. 5, Oct. 2005, pp. 1800—1810.
• Touraj Farahmand, Sassan Tabatabaei, Freddy Ben-Zeev, André Ivanov, “A DDJ Calibration Methodology for High-Speed Test and Measurement Equipments” International Test Conference 0-7803-9039-3 © 2005 IEEE, pdf
• Cristian Grecu, Partha Pande, Andre Ivanov, Resve Saleh, “Timing Analysis of Network on Chip Architectures for MP-SoC Platforms,” Microelectronics Journal, Elsevier Publications, Volume 36, Issue 9, September 2005, pp. 833-845.
• P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. de Micheli, “Design, Synthesis and Test of Networks on Chip: Challenges and Solutions,” IEEE Design and Test of Computers, Vol. 22, No. 5, Sept/Oct. 2005, pp. 404 – 413.
• P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh “Performance Evaluation and Design Trade-offs for Network-on-chip Interconnect Architectures,” IEEE Transactions on Computers, Vol. 54, No. 8, August 2005, pp. 1025 – 1040.
• Baosheng Wang, Yuejian Wu, Josh Yang, Andre Ivanov and Yervant Zorian, “SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms,” 23rd IEEE VLSI Test Symposium (VTS05), Rancho Mirage, Palm Springs, CA, USA, May 1st - May 5th, 2005
• Y. Maidon, T. Zimmer, E. Nold, A. Ivanov, “An Analog Circuit Fault Characterization Methodology,” Journal of Electronic Testing: Theory and Applications, Vol. 21, No. 2, April 2005, pp. 127—134.
• Baosheng Wang, Yuejian Wu and Andre Ivanov, “A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs,” Proc. Design Automation and Test in Europe (DATE 2005), Munich, Germany, Mar 7-11, 2005
• Baosheng Wang and André Ivanov, Time-Driven Embedded SRAM Testing Methodologies, in the Asia and South Pacific Design Automation Conference 2005 (ASP-DAC), PhD Forum, Shanghai, China, Jan. 18-21, 2005
• Baosheng Wang, Josh Yang, Yuejian Wu and André Ivanov, “A Retention-Aware Test Power Model for Embedded SRAM,” Proc. Asia and South Pacific Design Automation Conference 2005 (ASP-DAC), Shanghai, China, Jan. 18-21, 2005
• Baosheng Wang, Derek Ho, Samad Sheikhaei and André Ivanov, An Embedded Clock Infrastructure for SoC Path Delay Characterization, in the Second IEEE Workshop on Infrastructure IP (I-IP), Charlotte, NC, USA, Oct. 28 29, 2004
• A. Kuo, T. Farahmand, N. Ou, S. Tabatabaei, and A. Ivanov, “Jitter Models and Measurement Methods for High-Speed (Gb/s) Interconnects,” in IEEE International Test Conference (ITC), 2004.
• Baosheng Wang, Yuejian Wu and André Ivanov, Designs for Reducing Test Time of Distributed Small Embedded SRAMs, in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04), Cannes, France, Oct. 10-17, 2004
• Mohsen Nahvi and Andre Ivanov, “Indirect Test Architecture for SoC Testing,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23 , Issue 7, July 2004, pp. 1128 - 1142
• N. Ou, T. Farahmand, A. Kuo, S. Tabatabaei, and A. Ivanov, “Jitter Models for the Design and Test of High-Speed (Gb/s) Serial Interconnects,” IEEE Design and Test of Computers, vol. 21, Jul-Aug 2004.pp. 302 – 313.
• Baosheng Wang, Josh Yang, James Cicalo, André Ivanov and Zorian Yervant, “Reducing Embedded SRAM Test Time under Redundancy Constraints,” in the 22nd IEEE VLSI Test Symposium (VTS04), Napa Valley, CA, USA, Apr. 25-29, 2004
• Altet, J., Salhi, M.A., Dilhaire, S., Ivanov, A., “Calibration-free heat source localisation in ICs entirely covered by metal layers”; Electronics Letters, Volume: 40, Issue: 4, Feb. 2004, Pages:37-38
• Josh Yang, Baosheng Wang and Andre Ivanov, “Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode,” Proceedings of the 17th International Conference on VLSI Design, pp. 493-298, January 5-9, 2004.
• B. Wang, Y. B. Cho, S. Tabatabaei, A. Ivanov, “Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-offs for High-Speed Interconnect Device Testing,” in Proc. IEEE Twelfth Asian Test Symposium (ATS'2003), Nov. 17-19, 2003, pp. 348-353,
• J. Altet, M.A. Salhi, S. Dilhaire, A. Syal and A. Ivanov, “Localisation of devices acting as heat sources in ICs covered entirely by metal layers,” IEE Electronics Letters, 2 October 2003, Vol. 39, No. 20, pp. 1440 – 1441.
• B. Wang, J. Yang, A. Ivanov, “Reducing Test Time of Embedded SRAMs,” the 2003 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2003), pp. 47-52, July 28-29, 2003
• J. Altet, A. Ivanov, A. Wong, “Thermal Testing of Analogue Integrated Circuits: A Case Study,” Journal of Electronic Testing: Theory and Applications, Vol. 19, pp. 353-357, 2003.
• Mohsen Nahvi and Andre Ivanov, “An Embedded Autonomous Scan-Based Results Analyzer (EARA) for SoC Cores,” in proc. IEEE VLSI Test Symposium, 2003, pp. 293-298
• Zahra sadat Ebadi, Andre Ivanov, “Time Domain Multiplexed TAM: Implementation and Comparison” DATE, 2003 IEEE, pp. 732- 737 J. Altet, A. Ivanov, A. Wong, “Thermal Testing of Analogue Integrated Circuits: A Case Study,” Journal of Electronic Testing: Theory and Applications 19, 353-357, 2003
• F. Azais, A. Ivanov, M. Renovell, S. Tabatabaei, and Y. Bertrand, “A Unified Digital Test Technique for PLLs to Cover Catastrophic Faults,” IEEE Design and Test of Computers, Vol. 20, No. 1, Jan./Feb. 2003, pp. 60 – 67.
• F. Azaïz, Y. Bertrand, M. Renovell, A. Ivanov, S. Tabatabaei, “An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs” in the IEEE Design & Test of Computers - January-February 2003, pp. 60-67
• L. Hong, M. Nahvi, R. Fung, A. Ivanov, R. Saleh “Novel Test Methodologies for SoC/IP Design: Implementation and Comparison” IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff AB, July 2002, pp 20-30.
• S. Tabatabaei, A. Ivanov, “An Embedded Core for Sub-Picosecond Timing Measurements,” in proc. IEEE ITC Int. Test Conf., 2002, pp. 129-137
• M. Nahvi, A. Ivanov and R. Saleh, “Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores,” in proc. IEEE ITC Int. Test Conf., 2002, pp. 1176-1183
• Z. Zhao, A. Ivanov, “Embedded Servo Loop for ADC Linearity Testing,” Microelectronic Journal, Elsevier, Vol. 33, 2002, pp. 773 — 780.
• B. Alorda, A. Ivanov, and J. Segura, “An off-chip sensor circuit for On-Line transient current testing,” International On-Line Test Workshop 2002, France, July 2002.
• A. Syal, V. Lee, J. Altet and A. Ivanov, “CMOS Differential and Absolute Thermal Sensors,” Journal of Electronic Testing: Theory and Applications, Vol. 18, No. 3, June 2002, 295-304
• Sassan Tabatabaei, Andre Ivanov, “Embedded Timing Analysis: A SoC Infrastructure,” IEEE Design & Test of Computers, Infrastructure IP for SoCs, Vol 19, No. 3, May-June 2002, pp. 24-36
• Zahra sadat Ebadi, Andre Ivanov, “ Design of an Optimal Test Access Architecture under Power and Place-and-Route Constraints Using GA,” in Proc. IEEE Latin-American Test Workshop, pp. 154-159 , 2002.
• Zahra sadat Ebadi, Andre Ivanov, “ Design of an Optimal Test Access Architecture Using Genetic Algorithm,” Proc. IEEE Asian Test Symposium (ATS), pp. 205-210, 2001.
• Mohsen Nahvi, Andre Ivanov, “A Packet Switching Communication-Based Test Access Mechanism for System Chips,” in Proc. IEEE European Test Workshop, 2001, pp. 81-86
• A. Ivanov, S. Rafiq, M. Renovell, F. Azais, and Y. Bertrand, “On the Detectability of CMOS Floating Gate Transistor Faults,” IEEE Trans. Computer Aided Design of Circuits and Systems, Vol. 20, No. 1, Jan. 2001, pp. 116 --128.

• Frank Hutter, Domagoj Babic, Holger H. Hoos, and Alan J. Hu, “Boosting Verification by Automatic Tuning of Decision Procedures,” Formal Methods in Computer-Aided Design (FMCAD), 2007, to appear.
• Zvonimir Rakamaric, Roberto Bruttomesso, Alan J. Hu, and Alessandro Cimatti, “Verifying Heap-Manipulating Programs in an SMT Framework,” Automated Technology for Verification and Analysis: 5th International Symposium (ATVA), Lecture Notes in Computer Science Vol. 4762, pp. 237-252, Springer, 2007.
• Domagoj Babic, Alan J. Hu, Zvonimir Rakamaric, and Byron Cook, “Proving Termination by Divergence,” 5th IEEE International Conference on Software Engineering and Formal Methods (SEFM), 2007, to appear.
• Domagoj Babic, and Alan J. Hu, “Structural Abstraction of Software Verification Conditions,” Computer Aided Verification: 19th International Conference (CAV), Lecture Notes in Computer Science Vol. 4590, pp. 366-378, Springer, 2007.
• Flavio M. de Paula, and Alan J. Hu, “An Effective Guidance Strategy for Abstraction-Guided Simulation,” 44th ACM/IEEE Design Automation Conference (DAC), pp. 63-68, 2007.
• Zvonimir Rakamaric, Jesse Bingham, and Alan J. Hu, “An Inference-Rule-Based Decision Procedure for Verification of Heap-Manipulating Programs with Mutable Data and Cyclic Data Structures,” Verification, Model Checking, and Abstract Interpretation: 8th International Conference (VMCAI), Lecture Notes in Computer Science Vol. 4349, pp. 106-121, Springer, 2007.
• Domagoj Babic, Jesse Bingham, and Alan J. Hu, “B-Cubing: New Possibilities for Efficient SAT-Solving,” IEEE Transactions on Computers, Vol. 55, No. 11 (November 2006), pp. 1315-1324.
• Alan J. Hu, “High-Level vs. RTL Combinational Equivalence: An Introduction,” IEEE International Conference on Computer Design (ICCD), pp. 274-279, 2006.
• Flavio M. de Paula, and Alan J. Hu, “EverLost: A Flexible Platform for Industrial-Strength Abstraction-Guided Simulation,” Computer Aided Verification: 18th International Conference (CAV), Lecture Notes in Computer Science Vol. 4144, pp. 282-285, Springer, 2006.
• Xiushan Feng, and Alan J. Hu, “Early Cutpoint Insertion for High-Level Software vs. RTL Formal Combinational Equivalence Verification,” 43rd ACM/IEEE Design Automation Conference (DAC), 2006, pp. 1063-1068.
• David Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, and Sreeranga Rajan, “Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions,” International Journal of Parallel Programming, Vol.~34, No.~1 (March 2006), pp.~61--91.
• Domagoj Babic, Jesse D. Bingham, and Alan J. Hu, “B-Cubing Theory: New Possibilities for Efficient SAT-Solving,” 10th IEEE International High-Level Design Validation and Test Workshop (HLDVT), 2005, pp. 192-199.
• Xiushan Feng, and Alan J. Hu, “Cutpoints for Formal Equivalence Verification of Embedded Software,” 5th ACM International Conference on Embedded Software (EMSOFT), 2005, pp. 307-316.
• Domagoj Babic, Jesse D. Bingham, and Alan J. Hu, “Efficient SAT Solving: Beyond Supercubes,” 42nd ACM/IEEE Design Automation Conference (DAC), 2005, pp. 744-749.
• Jesse Bingham, and Alan J. Hu, “Empirically Efficient Verification for a Class of Infinite-State Systems,” Tools and Algorithms for the Construction and Analysis of Systems: 11th International Conference (TACAS), Lecture Notes in Computer Science Vol. 3440, pp. 77-92, Springer, 2005.
• Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, David A. Wood, “Improving Multiple-CMP Systems Using Token Coherence,” IEEE 11th International Symposium on High-Performance Computer Architecture (HPCA), IEEE Press, 2005, pp. 328-339.
• Xiushan Feng, Alan J. Hu, and Jin Yang, “Partitioned Model Checking from Software Specifications,” Asia South Pacific Design Automation Conference (ASPDAC), IEEE Press, 2005, pp. 583-587.
• Domagoj Babic, and Alan J. Hu, “Integration of Supercubing and Learning in a SAT Solver,” Asia South Pacific Design Automation Conference (ASPDAC), IEEE Press, 2005, pp. 438-444.
• Kelvin Ng, Alan J. Hu, and Jin Yang, “Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs,” IEEE International Conference on Computer Design (ICCD), IEEE Computer Society Press, 2004, pp. 488-492.
• Drew Dean, and Alan J. Hu, “Fixing Races for Fun and Profit: How to use access(2),” 13th USENIX Security Symposium, 2004, pp. 195-206.
• Jesse Bingham, Anne Condon, Alan J. Hu, Shaz Qadeer, and Zhichuan Zhang, “Automatic Verification of Sequential Consistency for Unbounded Addresses and Data Values,” Computer Aided Verification: Sixteenth International Conference (CAV), Lecture Notes in Computer Science Vol. 3114, pp. 427-439, Springer, 2004.
• Alan J. Hu, Jeremy Casas, and Jin Yang, “Efficient Generation of Monitor Circuits for GSTE Assertion Graphs,” IEEE/ACM International Conference on Computer-Aided Design, 2002.
• Alan J. Hu, Jeremy Casas, and Jin Yang, “Reasoning about GSTE Assertion Graphs,” 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), 2003, to be published in Lecture Notes in Computer Science , Springer.
• Anne E. Condon and Alan J. Hu, “Automatable Verification of Sequential Consistency,” Theory of Computing Systems, Volume 36, Number 5, September 2003, Springer-Verlag, pp. 431-460.
• Jesse D. Bingham, Anne E. Condon, and Alan J. Hu, “Towards a Decidable Notion of Sequential Consistency,” 15th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), pp. 304-313, ACM Press, 2003.
• Jesse D. Bingham, and Alan J. Hu, “Semi-Formal Bounded Model Checking,” Computer Aided Verification: Fourteenth International Conference, Lecture Notes in Computer Science Vol. 2404, pp. 280-294, Springer, 2002.
• Xiushan Feng, and Alan J. Hu, “Automatic Formal Verification for Scheduled VLIW Code,” ACM SIGPLAN Joint Conference: Languages, Compilers, and Tools for Embedded Systems, and Software and Compilers for Embedded Systems, pp. 85-92, ACM Press, 2002.
• Marcio T. Oliveira, and Alan J. Hu, “High-Level Specification and Automatic Generation of IP Interface Monitors,” 39th ACM/IEEE Design Automation Conference, pp. 129-134, IEEE Press, 2002.
• Tim Braun, Anne Condon, Alan J. Hu, Kai S. Juse, Marius Laza, Michael Leslie, and Rita Sharma, “Proving Sequential Consistency by Model Checking,” IEEE International High-Level Design, Validation, and Test Workshop, pp. 103-108, 2001.
• Felix Sheng-Ho Chang and Alan J. Hu, “Fast Specification of Cycle-Accurate Processor Models,” IEEE International Conference on Computer Design, pp. 488-492, 2001.
• Alvin R. Albrecht and Alan J. Hu, “Register Transformations with Multiple Clock Domains,” 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods, 2001, published in Springer Lecture Notes in Computer Science Vol. 2144, pp. 126-139, 2001.
• Anne E. Condon and Alan J. Hu, “Automatable Verification of Sequential Consistency,” 13th ACM Symposium on Parallel Algorithms and Architectures, pp. 113-121, 2001.
• Kanna Shimizu, David L. Dill, and Alan J. Hu, “Monitor-Based Formal Specification of PCI,” Formal Methods in Computer-Aided Design, 2000, published in Springer Lecture Notes in Computer Science Vol. 1954, pp. 335-353, 2000.
• Brian D. Winters and Alan J. Hu, “Source-Level Transformations for Improved Formal Verification,” IEEE International Conference on Computer Design, pp. 599-602, 2000.
• David W. Currie, Alan J. Hu, Sreeranga Rajan, and Masahiro Fujita, “Automatic Formal Verification of DSP Software,” 37th ACM/IEEE Design Automation Conference, pp. 130-135, 2000.