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FPGA 2002

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Checkerboard Results Two layout tiles are used, each using the disjoint switch block layout structure. "Black square" switch blocks are chosen to increase diversity by mapping track t to t+/-1. Other "black square" switch blocks produce similar results. Normalized Results disjoint switch block, 6 LUTs per cluster Checkerboard Min Chan. Width Area Delay 4-input LUTs no 1.0 1.0 1.0 yes 0.994 0.995 1.003 5-input LUTs no 1.0 1.0 1.0 yes 0.969 0.987 1.017 6-input LUTs no 1.0 1.0 1.0 yes 0.984 0.996 0.997