Cache Simulator
Download: https://github.com/jfunston/MultiCacheSim
I wrote a cache simulator designed to be used with memory access traces obtained from Pin. It has been optimized for performance and can process large inputs (100s of GBs) in a few hours depending on configuration.
Features:
•Configurable size, associativity, and line size
•MOESI protocol simulation for multiple caches
•Tracking of miss and data source statistics
•NUMA statistics are maintained based off of a fist-touch policy and configurable page size
•Virtual-to-physical address translation
•Prefetcher "plugins"
–Adjacent line prefetcher
–Sequential prefetcher (similar to AMD's L1 prefetcher)
•LRU replacement policy
Contact Info:
Email: jfunston@ece.ubc.ca