00001 /* Netlist to be placed stuff. */ 00002 int num_nets, num_blocks; 00003 struct s_net *net; 00004 struct s_block *block; 00005 boolean *is_global; 00006 00007 /* Physical FPGA architecture stuff */ 00008 int nx, ny; 00009 00010 /* chan_width_x is the x-directed channel; i.e. between rows */ 00011 int *chan_width_x, *chan_width_y; /* numerical form */ 00012 struct s_grid_tile **grid; 00013 00014 /* [0..num_nets-1] of linked list start pointers. Defines the routing. */ 00015 struct s_trace **trace_head, **trace_tail; 00016 00017 /* Structures to define the routing architecture of the FPGA. */ 00018 int num_rr_nodes; 00019 t_rr_node *rr_node; /* [0..num_rr_nodes-1] */ 00020 t_ivec ***rr_node_indices; 00021 int num_rr_indexed_data; 00022 t_rr_indexed_data *rr_indexed_data; /* [0 .. num_rr_indexed_data-1] */ 00023 int **net_rr_terminals; /* [0..num_nets-1][0..num_pins-1] */ 00024 struct s_switch_inf *switch_inf; /* [0..det_routing_arch.num_switch-1] */ 00025 int **rr_blk_source; /* [0..num_blocks-1][0..num_class-1] */
1.6.1