00001
00019 #include "fpgaInt.h"
00020
00024
00025 static int Fpga_NodeVecCompareLevels( Fpga_Node_t ** pp1, Fpga_Node_t ** pp2 );
00026
00030
00042 Fpga_NodeVec_t * Fpga_NodeVecAlloc( int nCap )
00043 {
00044 Fpga_NodeVec_t * p;
00045 p = ALLOC( Fpga_NodeVec_t, 1 );
00046 if ( nCap > 0 && nCap < 16 )
00047 nCap = 16;
00048 p->nSize = 0;
00049 p->nCap = nCap;
00050 p->pArray = p->nCap? ALLOC( Fpga_Node_t *, p->nCap ) : NULL;
00051 return p;
00052 }
00053
00065 void Fpga_NodeVecFree( Fpga_NodeVec_t * p )
00066 {
00067 FREE( p->pArray );
00068 FREE( p );
00069 }
00070
00082 Fpga_Node_t ** Fpga_NodeVecReadArray( Fpga_NodeVec_t * p )
00083 {
00084 return p->pArray;
00085 }
00086
00098 int Fpga_NodeVecReadSize( Fpga_NodeVec_t * p )
00099 {
00100 return p->nSize;
00101 }
00102
00114 void Fpga_NodeVecGrow( Fpga_NodeVec_t * p, int nCapMin )
00115 {
00116 if ( p->nCap >= nCapMin )
00117 return;
00118 p->pArray = REALLOC( Fpga_Node_t *, p->pArray, nCapMin );
00119 p->nCap = nCapMin;
00120 }
00121
00133 void Fpga_NodeVecShrink( Fpga_NodeVec_t * p, int nSizeNew )
00134 {
00135 assert( p->nSize >= nSizeNew );
00136 p->nSize = nSizeNew;
00137 }
00138
00150 void Fpga_NodeVecClear( Fpga_NodeVec_t * p )
00151 {
00152 p->nSize = 0;
00153 }
00154
00166 void Fpga_NodeVecPush( Fpga_NodeVec_t * p, Fpga_Node_t * Entry )
00167 {
00168 if ( p->nSize == p->nCap )
00169 {
00170 if ( p->nCap < 16 )
00171 Fpga_NodeVecGrow( p, 16 );
00172 else
00173 Fpga_NodeVecGrow( p, 2 * p->nCap );
00174 }
00175 p->pArray[p->nSize++] = Entry;
00176 }
00177
00189 int Fpga_NodeVecPushUnique( Fpga_NodeVec_t * p, Fpga_Node_t * Entry )
00190 {
00191 int i;
00192 for ( i = 0; i < p->nSize; i++ )
00193 if ( p->pArray[i] == Entry )
00194 return 1;
00195 Fpga_NodeVecPush( p, Entry );
00196 return 0;
00197 }
00198
00210 Fpga_Node_t * Fpga_NodeVecPop( Fpga_NodeVec_t * p )
00211 {
00212 return p->pArray[--p->nSize];
00213 }
00214
00226 void Fpga_NodeVecWriteEntry( Fpga_NodeVec_t * p, int i, Fpga_Node_t * Entry )
00227 {
00228 assert( i >= 0 && i < p->nSize );
00229 p->pArray[i] = Entry;
00230 }
00231
00243 Fpga_Node_t * Fpga_NodeVecReadEntry( Fpga_NodeVec_t * p, int i )
00244 {
00245 assert( i >= 0 && i < p->nSize );
00246 return p->pArray[i];
00247 }
00248
00260 int Fpga_NodeVecCompareLevels( Fpga_Node_t ** pp1, Fpga_Node_t ** pp2 )
00261 {
00262 int Level1 = Fpga_Regular(*pp1)->Level;
00263 int Level2 = Fpga_Regular(*pp2)->Level;
00264 if ( Level1 < Level2 )
00265 return -1;
00266 if ( Level1 > Level2 )
00267 return 1;
00268 if ( Fpga_Regular(*pp1)->Num < Fpga_Regular(*pp2)->Num )
00269 return -1;
00270 if ( Fpga_Regular(*pp1)->Num > Fpga_Regular(*pp2)->Num )
00271 return 1;
00272 return 0;
00273 }
00274
00286 void Fpga_NodeVecSortByLevel( Fpga_NodeVec_t * p )
00287 {
00288 qsort( (void *)p->pArray, p->nSize, sizeof(Fpga_Node_t *),
00289 (int (*)(const void *, const void *)) Fpga_NodeVecCompareLevels );
00290 }
00291
00303 int Fpga_NodeVecCompareArrivals( Fpga_Node_t ** ppS1, Fpga_Node_t ** ppS2 )
00304 {
00305 if ( (*ppS1)->pCutBest->tArrival < (*ppS2)->pCutBest->tArrival )
00306 return -1;
00307 if ( (*ppS1)->pCutBest->tArrival > (*ppS2)->pCutBest->tArrival )
00308 return 1;
00309 return 0;
00310 }
00311
00323 void Fpga_SortNodesByArrivalTimes( Fpga_NodeVec_t * p )
00324 {
00325 qsort( (void *)p->pArray, p->nSize, sizeof(Fpga_Node_t *),
00326 (int (*)(const void *, const void *)) Fpga_NodeVecCompareArrivals );
00327
00328 }
00329
00330
00342 void Fpga_NodeVecUnion( Fpga_NodeVec_t * p, Fpga_NodeVec_t * p1, Fpga_NodeVec_t * p2 )
00343 {
00344 int i;
00345 Fpga_NodeVecClear( p );
00346 for ( i = 0; i < p1->nSize; i++ )
00347 Fpga_NodeVecPush( p, p1->pArray[i] );
00348 for ( i = 0; i < p2->nSize; i++ )
00349 Fpga_NodeVecPush( p, p2->pArray[i] );
00350 }
00351
00363 void Fpga_NodeVecPushOrder( Fpga_NodeVec_t * vNodes, Fpga_Node_t * pNode, int fIncreasing )
00364 {
00365 Fpga_Node_t * pNode1, * pNode2;
00366 int i;
00367 Fpga_NodeVecPush( vNodes, pNode );
00368
00369 for ( i = vNodes->nSize-1; i > 0; i-- )
00370 {
00371 pNode1 = vNodes->pArray[i ];
00372 pNode2 = vNodes->pArray[i-1];
00373 if ( fIncreasing && pNode1->pCutBest->tArrival >= pNode2->pCutBest->tArrival ||
00374 !fIncreasing && pNode1->pCutBest->tArrival <= pNode2->pCutBest->tArrival )
00375 break;
00376 vNodes->pArray[i ] = pNode2;
00377 vNodes->pArray[i-1] = pNode1;
00378 }
00379 }
00380
00392 void Fpga_NodeVecReverse( Fpga_NodeVec_t * vNodes )
00393 {
00394 Fpga_Node_t * pNode1, * pNode2;
00395 int i;
00396 for ( i = 0; i < vNodes->nSize/2; i++ )
00397 {
00398 pNode1 = vNodes->pArray[i];
00399 pNode2 = vNodes->pArray[vNodes->nSize-1-i];
00400 vNodes->pArray[i] = pNode2;
00401 vNodes->pArray[vNodes->nSize-1-i] = pNode1;
00402 }
00403 }
00404
00408