Re: ELEC379 Asgn 5

Ed Casas (edc@ece.ubc.ca) Mon, 29 Mar 1999 20:47:23 -0800 

Date: Mon, 29 Mar 1999 20:47:23 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: ELEC379 Asgn 5



A student asked:

> Can I ask you if I have to include timing requirements such as
> the delay time for signals like the MSTRB on the CPU read
> cycle?

MSTRB is a CPU output.  CPU timing specifications measured to
MSTRB are thus guaranteed responses, not requirements.  Since
MSTRB is not connected to either of the memory chips it will not
figure in any expressions for the other chip's requirements
either.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592