Re: Lab 3

Ed Casas (edc@ece.ubc.ca) Wed, 24 Feb 1999 18:24:04 -0800 

Date: Wed, 24 Feb 1999 18:24:04 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Lab 3



A student asked:

> I am having a small problem with LAb 3.  In the lab it states
> that the clock divider should be implemented as a separate
> entity and used as a component in the main timer description.
> I don't understand how to go about this.  Does the architecture
> of the clock divider appear in a separate file which is then
> included in the main program?

Yes.  See the description and example in Lecture 7, page 2 and
the very top of page 3.

> Whenever components were mentioned in our class notes, only the
> port assignments were shown.  I am not sure where the actual
> architecture of the device appears or how it is used in the
> main program.

Look at the example again.  It shows 3 files that are used as
follows:

        mypackage.vhd - component declaration
        parity.vhd - component instantiation
        xor2.vhd - component entity/architecture

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592