Re: Assignment 3

kevin Oldknow (koldknow@mech.ubc.ca) Tue, 23 Feb 1999 10:49:02 -0800 

From: "kevin Oldknow" <koldknow@mech.ubc.ca>
Subject: Re: Assignment 3
Date: Tue, 23 Feb 1999 10:49:02 -0800




I have been assuming that the memory output should be set to high impedence during a write cycle to avoid an ill-defined value at the output.  Anyone else?

Kevin Oldknow
Mechanical Engineering
    -----Original Message-----
    From: Bo Min Jiang <bmjiang@unixg.ubc.ca>
    To: elec379@casas.ece.ubc.ca <elec379@casas.ece.ubc.ca>
    Date: February 23, 1999 10:40 AM
    Subject: Re: Assignment 3
    
    
    For the memory component, since there are separate data in and data out signals, does that mean data can be written to and read from the memory simultaneously?
    
    Bo Min Jiang
    Engineering Physics, 4th Year
    University of British Columbia