Re: timing diagram

Ed Casas (edc@ece.ubc.ca) Wed, 6 Dec 2000 21:57:48 -0800 

Date: Wed, 6 Dec 2000 21:57:48 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: timing diagram



> Please explain the timing diagram for read and write cycles. For example, 
> why is there 2 signals for the address bus? And is there a significant 
> meaning when they cross?

The two levels signify that the signal(s) can be either high or
low but cannot change (are steady) between the transitions.

The transitions indicate signal changes.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592