Assignment #4

Marc Lee (marclwn@home.com) Fri, 8 Dec 2000 22:42:23 -0800 

From: "Marc Lee" <marclwn@home.com>
Subject: Assignment #4
Date: Fri, 8 Dec 2000 22:42:23 -0800




Hi,

I have two questions about timing analysis on question #3.

For signal tRC of SRAM read cycle, tWC of SRAM write cycle, and tRC of flash read cycle, their expressions of guaranteed responses are all 4C (160ns) as stated on the solution handout. Does this mean that the microprocessor is always reading for a certain CPU cycle and writing for the next CPU cycle? Couldn't the microprocessor read or write for more than 2 consecutives cycles instead?

Also, it looks to me that the width of a signal on the address bus equals to t41+t46+t42 (all of these three are guaranteed responses) on figure 17 of the Intel386EX datasheet. Again, why signals tRC of SRAM read cycle, tWC of SRAM write cycle, and tRC of flash read cycle all have expressions 4C (160ns), but not t41+t46+t42 (70ns)?



Marc