Greg Frey (gregf@unixg.ubc.ca) Tue, 28 Nov 2000 21:04:34 -0800
- Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
- New Message to:eece379@listhost.ece.ubc.ca
- Reply to:Assignment 4 - Q1&2
- Next message: Ed Casas: "Re: Assignment 4 - Q1&2"
- Previous message: Ed Casas: "Re: OE and RD"
- Next in thread: Ed Casas: "Re: Assignment 4 - Q1&2"
- Reply: Ed Casas: "Re: Assignment 4 - Q1&2"
From: "Greg Frey" <gregf@unixg.ubc.ca> Subject: Assignment 4 - Q1&2 Date: Tue, 28 Nov 2000 21:04:34 -0800I don't see how the memory devices we are given in Q1 can completely fill the address space spanned by the given 20-bit CPU address bus. If so, how can I completely decode the CPU addresses for Q2 ? Do we need to add extra RAM and ROM banks for Q2 ? ( I calculate 2^16 + 2^17 bytes in the given memory, but I think we need 2^20.....so have I screwed up somewhere?) Thanks. ------------------------------------------------------ Greg Frey gregf@unixg.ubc.ca
- Next message: Ed Casas: "Re: Assignment 4 - Q1&2"
- Previous message: Ed Casas: "Re: OE and RD"
- Next in thread: Ed Casas: "Re: Assignment 4 - Q1&2"
- Reply: Ed Casas: "Re: Assignment 4 - Q1&2"