Re: Assignment 2: Loops

Ed Casas (edc@ece.ubc.ca) Mon, 6 Nov 2000 09:58:42 -0800 

Date: Mon, 6 Nov 2000 09:58:42 -0800
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: Assignment 2: Loops



> As per the second assignment, is it valid to use combinational
> and sequential loop statements to generate register assignments
> for the RAM module?

No.  You do not need loop statements of any sort to instantiate
RAM.  See the example in the course notes.

VHDL does have loop statements (both the concurrent "for
generate" and the sequential "for loop" that can generate
multiples instances of logic (e.g. registers), but you are not
allowed to use them in this course (the reasons why I've
restricted the subset of VHDL you can use have been covered
earlier).

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592