Lab 2

Greg Frey (gregf@unixg.ubc.ca) Fri, 20 Oct 2000 01:35:40 -0700 

From: "Greg Frey" <gregf@unixg.ubc.ca>
Subject: Lab 2
Date: Fri, 20 Oct 2000 01:35:40 -0700




Now for something completely different:

For lab 2, do we assume that the input from the keyboard is always a valid
input (0, 1, 2, 3, or 4)?
If not, how should we deal with an invalid input? We can either reject it in
the assembly language part or in the VHDL part (although I think we would
have to deviate from a straight-up implementation of the figure on page 3).
I don't see this discussed anywhere in the lab handout.

Also, do you want a prompt given to the user?

Thanks.

----------------------------------------
Greg Frey
gregf@unixg.ubc.ca