Re: If Statements

Ed Casas (edc@ece.ubc.ca) Mon, 25 Sep 2000 07:52:34 -0700 

Date: Mon, 25 Sep 2000 07:52:34 -0700
From: Ed Casas <edc@ece.ubc.ca>
Subject: Re: If Statements



> The course notes states that we are only allowed to use
> single-if structures, am I to interpret that we are allowed to
> use multiple if statements in our code and are not allowed to
> use nested if statements?

NO!

The only change you may make to the template in the course notes
is to change the names of the signals (clk, q and d) to something
that applies to you.  The only exception I mentioned is that you
may include multiple simple assignments (a<=b;) within the single
if.

> ie. are we allowed to do the following:
> 
> 	process(clk)
> 	begin
> 		if clk'event and clk = '1' then
> 			foo <= something;
> 		end if;
> 		if something_else = '1' then
> 			foo <= something_totally_different;
> 		end if;
> 	end process;

NO!

Re-read the notice that is in bold on page 7 of Lecture 1:

	In this course you may only use processes to generate
	registers and may only use the single-if structure shown
	below.

It says "single-if" and "to generate registers only."  Your
example has two if statements and (depending on what
"something_else" is) could generate logic other than registers.

I've already spent a significant amount of time explaining the
reasons for this in the lectures (it's a coding style that allows
for a clear mapping between the VHDL and the synthesized
hardware).  

This particular restriction makes it easier for you to see the
separation between combinational and sequential logic.

To get the most benefit out of this course you should try to
understand the reasons behind the method rather than trying to
figure out ways around it.

-- 
Ed Casas   edc@ece.ubc.ca   http://casas.ece.ubc.ca   +1 604 822-2592