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- Welcome to EECE 379 Ed Casas
- Re: Welcome to EECE 379 Steve Chou
- Re: Welcome to EECE 379 Ed Casas
- Re: Welcome to EECE 379 Shawn O'Neill
- Re: A question about the assignment Ed Casas
- Ass#1 Shawn O'Neill
- ASS #1 Eric Wei
- Re: error message Eric Wei
- Re: error message ddowler
- VHDL 1987 or VHDL 1993? Kelvin Ng
- Re: VHDL 1987 or VHDL 1993? Ed Casas
- Re: Assignment 1 due time Ed Casas
- Lab #3 counter question Kim Bozman
- lab03 - compile package file Stephen Shang
- Re: lab03 - compile package file Ed Casas
- lab4 plin@ece.ubc.ca
- Re: help Eric Wei
- Re: help Kelvin Ng
- Re: help Ed Casas
- To Prof. Casas D.D. R.
- Reserving Memory ddowler
- Re: Reserving Memory Stephen Shang
- Re: Reserving Memory Eric Wei
- buffer Jonathan Lashin
- Re: buffer Eric Wei
- Re: buffer Ed Casas
- Marks Breakdown for Assignment 1&2 Preston Cheung
- the IN instruction Andrew Yung
- Re: Marks Breakdown for Assignment 1&2 Ed Casas
- Re: the IN instruction Kim Bozman
- Re: lab4 [now available] Ed Casas
- Marking of assignment 2 Jonathan Lashin
- Re: Marking of assignment 2 Ed Casas
- Re: Marking of assignment 2 ddowler
- Re: Marking of assignment 2 Ed Casas
- Assignment #3 adam lazareck
- lab4: what is the idle signal? plin@ece.ubc.ca
- Assignment 3-- Stack Register Steve Chou
- Re: Assignment #3 Ed Casas
- Re: lab4: what is the idle signal? Ed Casas
- Re: Assignment 3-- Stack Register Ed Casas
- Re: assignment #3 part 1 Ed Casas
- SBC/FPGA Shawn O'Neill
- Vague Specs Shawn O'Neill
- Asg 3 ddowler
- The ROM David Ma
- Assignment3 Jonathan Lashin
- Re: SBC/FPGA Ed Casas
- Re: Assignment3 Ed Casas
- Re: The ROM Ed Casas
- Re: Vague Specs Ed Casas
- Duplicate Instructions? ddowler
- Testing ddowler
- Re: Duplicate Instructions? Ed Casas
- Re: Testing Ed Casas
- Midterm Craig Amendt
- cpu_package file Craig Amendt
- Re: cpu_package file Ed Casas
- MIDTERM ddowler
- Re: MIDTERM Eric Wei
- Midterm Jonathan Lashin
- Re: I still get the bus contention. Ed Casas
- in lab4, I have bus content. SIMON SUN
- Re: in lab4, I have bus content[ion] Ed Casas
- LAB 4 ddowler
- Re: LAB 4 Ed Casas
- Lab4 Jonathan Lashin
- Lab Jonathan Lashin
- I still get the bus contention. Xin Sun
- Re: Lab4 James Wu
- Defining enumerated types in MaxPlus II James Wu
- Re: Defining enumerated types in MaxPlus II Chris
- Re: Lab Ed Casas
- Re: status port Eric Wei
- Re: status port Ed Casas
- Re: old labs and assigments Ed Casas
- Assignment3 : 3 ways to design ROM Jun Wang
- Re: Assignment3 : 3 ways to design ROM Ed Casas
- Re: EE 379 participation markss Ed Casas
- Lab 4 Report Leonardo C Castro
- lab5 Avideh Shahabi
- Lab5 Jonathan Lashin
- possible change to course marking scheme Ed Casas
- Re: Lab 4 Report Ed Casas
- midterm (to Dr Casas) pwp lau
- about the ass5 timing requirement Xin Sun
- ASS5 ddowler
- Re: ASS5 Ed Casas
- Asg5 Stephen Shang
- Re: Asg5 Ed Casas
- # of words per chip Po Wah Peter Lau
- assignemnt 5 Po Wah Peter Lau
- address decoder Carmen Lee
- (no subject) pwplau
- Re: [Asg 5: number of CS signals] Ed Casas
- Re: assignemnt 5 Ed Casas
- Re: address decoder Ed Casas
- Re: # of words per chip Ed Casas
- Address range of the RAM system in Q.1? Kelvin Ng
- Re: Address range of the RAM system in Q.1? Ed Casas
- assignment5 question1 A
- assignment5 question1 A
- assignment5 question1 A
- assignment5 question1 Po Wah Peter Lau
- Re:assignment5 question1 Jonathan Lashin
- Assignment #5: what does the clock have to do with it? Andrew Ching Hong Yung
- Re: Assignment #5: what does the clock have to do with it? Ed Casas
- Final Questions Jonathan Lee
- Assignment 5 solutions Kyle MacDonald
- Re: Assignment 5 Solutions Jonathan Lashin
- A question MAY SIKSIK
- Re: A question csimpson@ieee.org
- Re: Office Hours Ed Casas
- Questions about system bus Pauline Siu
- Re: Questions about system bus Ed Casas
- Question about serial interface FENN CORWIN HO MING
- Re: Question about serial interface Ed Casas
- timing stuff ddowler
- Memory design harry lee
- final Craig Amendt
- Re: final Ed Casas
- Re: timing stuff Ed Casas
- FPGAs Simon Tang
- Assignment 5 Matt Lai
- Re: FPGAs Craig Amendt
- T or F questions Xin Sun
- Serial Device Interface Duncan Chou
- data transfer in serial interface Hui John
- Re: Serial Device Interface Ed Casas
- Re: T or F questions Ed Casas
- Re: FPGAs Ed Casas
- Re: Assignment 5 Ed Casas
- question about the lab marks Ed wun
- Midterm weight Howard Chan
- Open-collector Barry Kwok
- room change? Simon Lee
- (no subject) Shui Fai Yau
- Re: Memory design Ed Casas
- Re: data transfer in serial interface Ed Casas
- Re: question about the lab marks Ed Casas
- Re: Midterm weight Ed Casas
- Re: Open-collector Ed Casas
- Re: your mail Ed Casas
- Re: your mail [memory decoder] Ed Casas
- PCI bus csimpson@ieee.org
- Re: PCI bus Ed Casas
- Please check your EECE 379 mark Ed Casas
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