The numbers in parentheses indicate the number of marked items (1
mark each).

			      Labs

Lab 1 Pre-Lab (4)

- name, date and lab number on first page
- 3 reasonably complete verilog files
- name and date in each files' comments
- 3 simulation waveforms


Lab 1 Report (3)

- listing of working verilog code
- schematic
- compilation summary

Lab 2 Pre-Lab (4)

- 3 reasonably complete verilog source files (1 mark each)
- simulation results showing *all* tests passing

Lab 2 Report (4)

- name, date and lab number on first page
- four verilog source files
- four schematics
- compilation summary

Lab 3 Pre-Lab (4)

- tonegen.sv listing
- testbench waveforms
- toneplayer.c listing
- toneplayer.c output

Lab 3 Lab (3)

- tonegen.sv and tonegen.c listing
- compilation report
- schematic

Lab 3 Pre-Lab (4)

- tonegen.sv listing
- testbench waveforms
- toneplayer.c listing
- toneplayer.c output

Lab 3 Lab (3)

- tonegen.sv and tonegen.c listing
- compilation report
- schematic

Lab 4 Pre-Lab (4)

- reasonable approximation of spimaster.sv source
- testbench output
- completed C code
- test output showing register initializations

Lab 4 Report (3)

- spimaster.sv and lab4.c listings
- compilation report
- screen capture showing a CPU and spimaster module

Lab 5 Pre-Lab (2)

- Verilog code for myfifo.sv
- testbench output

Lab 5 Report (3)

- myfifo.sv listing
- compilation report
- screen capture showing x/y values being printed
- SignalTap screen capture for odata=xxxx07ff (or thereabouts)


			   Assignments

Assignment 1 (6)

Q1 (4.3 and 4.4)

- correct code for 4-input XOR

- simulation output showing the error detected (most people
  failed to include this)

Q2 (4.22)

- reasonable code

Q3 (4.48 and 4.49)

- 4.48: yes, same function
- 4.49: no, different 

  (many people drew the circuits correctly but failed to answer
  the questions thus getting zero for this question)

Q4 (4.27)

- simulation results showing output inverts when J=K=1

Assignment 2 (4)

Q1

- listing of a Verilog testbench
- listing some sort of simulation results showing the testbench runs
- a simulation transcript that shows a comparison of expected and
  computed values
- the correct largest error (for the given test vectors,
  approximately 5 or 5/32768=152E-6)

Assignment 3 (5)

- only output signal is DOUT
- tDS from DIN to SCLK
- tDH from SCLK to DIN
- tDS and tDH are minimum of 10 ns
- tDS SDC: uses set_output_delay statement (-0.5 if not labelled)


			     Project

Abstract (2)

- team member names
- project objectives

Proposal (5)

- high-level description
- block diagrams
- parts list
- milestones

[lack of references was not penalized due to ambiguous language
in the requirements]

Unfortunately, since each project is different the marking for
the following is somewhat subjective.  These are rough guidelines
on how I judged the project work.

Originality (out of 5):

  highly original: 5
  some original aspects: 4
  not original: 3
  plagiarized: 0
  
Accomplishment (scope+completion) (out of 5):

  the expected amount of original work; succesfully completed: 5
  almost enough original work, successfully completed: 4
  less than the expected amount of work, or significant objectives incomplete: 3
  final design not working: 2
  no/little effort demonstrated: 0/1

Final Report (out of 5):

  clearly-written, error-free, complete: 5
  substantially complete: 4
  substantial omissions or other errors: 3
  minimal effort: 2
  nothing or almost nothing submitted: 0/1
    
Demonstration (out of 5):

  well-planned, engaging: 5
  informative: 4
  good effort: 3
  showed something: 2
  missed the demo: 0


			  Mid-Term Exam

One mark was assigned for each of the following essential
elements of a correct solution:

Question 1 (9)

- half a mark for each correct width and value

Question 2 (7)

- clk starts at 0
- clk inverts every 1us
- x takes on values 1,3,5 or 0,1,2 (2 marks, -1 per error)
- display shows 1,3 or 0,1
- y takes on values 2,4,6 or 1,0,3 (2 marks, -1 per error)

Question 3 (Part 2, Question 1)

- deduct 0.5 for a small error (e.g. syntax)
- deduct 1 for a serious error (would give wrong result)

Question 4 (Part 2, Question 2)

- deduct 0.5 for a small error (e.g. syntax)
- deduct 1 for a serious error (would give wrong result)

			   Final Exam

Q1 (7)

1 mark per table row (1/2 for size, 1/2 for value)

Q2 (4)

- set values at t=0
- set values at t=30, 40
- change values every 20ns for ca, cb

Q3 (6)

- labelled inputs and outputs
- a, b registers
- output register
- reset muxes
- a,b adders
- c adder

Q4 (7)

- next-state logic for state (3)
- next-state logic for pulse
- alway_ff block
- registered output
- registered state transition

Q5 (8)

- each r/g (4)
- max fclk
- delay -> setup time calculation
- value
- hold time